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Datasheet File OCR Text:

MT312 Satellite Channel Decoder Design Manual
Part Number:
MT312
August 2003
Issue Date:
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MT312 Table of Contents
Design Manual
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Additional Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Viterbi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 De-Interleaver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Reed-Solomon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 De-Scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Application Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.0 Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.0 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 Analogue-to-Digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 QPSK demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4 Forward error correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4.1 Viterbi error count measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4.1.1 Viterbi error count coarse indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4.2 The frame alignment block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.4.3 The De-interleaver block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.4.3.1 DVB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.4.3.2 DSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.4.4 The Reed-Solomon decoder block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.4.5 The energy dispersal (de-scrambler) block, DVB only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.4.6 Output stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.5 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.5.1 Symbol Rate and Code Rate Search Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.6 DiSEqCTM Transmit and Receive Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.6.1 DiSEqCTM transmitting messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.6.2 DiSEqCTM receiving messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.0 MT312 software control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1 MT312 register map overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2 Register usage overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.0 MT312 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1 Initialization sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2 The configuration register (127) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.3 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.4 Spectral inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.5 Read/write registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.5.1 Reset register 21 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.5.2 System clock frequency register 34 (R/W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.6 Read registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.6.1 Identification register 126 (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.0 Tuner Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1 Simple channel change sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2 Channel change sequence with a new symbol rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.3 Channel change sequence with search mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.4 Tuner Control Read/Write Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.4.1 General purpose port control register 20 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.4.2 FR_LIM frequency limit register 37 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.4.3 FR_OFF frequency offset register 38 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.5 Tuner Control Read Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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5.5.1 Measured LNB frequency error registers 7 - 8 (R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.5.2 Frequency error 1 and 2 registers 111 - 115 (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.0 DiSEqC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.1 Screen printouts of DiSEqCTM waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.2 DiSEqCTM control read/write registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.2.1 DISEQC mode control register 22 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.2.2 DISEQC ratio register 35 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.2.3 DISEQC instruction register 36 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.2.4 DISEQC2 control 1 registers 121 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.2.5 DISEQC2 Control 2 registers 122 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.3 DiSEqC Control Read Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.3.1 DISEQC2 Interrupt Indicators register 118 (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.3.2 DISEQC2 Status Indicators register 119 (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.3.3 DISEQC2 FIFO register 120 (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.0 QPSK demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.1 QPSK Demodulator Read/Write Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.1.1 Symbol rate registers 23 - 24 (R/W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.1.2 Viterbi mode register 25 (R/W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.1.3 QPSK control register 26 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.1.4 Go command register 27 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.1.5 QPSK interrupt output enable registers 28 - 30 (R/W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.1.6 QPSK status output enable register 32 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.2 QPSK Demodulator Read Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.2.1 QPSK Interrupt registers 0 - 2 (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.2.2 QPSK Status registers 4 - 5 (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.2.3 Symbol Rate Output registers 116 - 117 (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.2.4 Monitor registers 123 - 124 (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8.0 Forward Error Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8.1 Forward error correction read/write registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8.1.1 FEC interrupt enable register 31 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8.1.2 FEC_STATUS output enable register 33 (R/W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.1.3 FEC setup register 97 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.2 Forward Error Correction Read Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 8.2.1 FEC interrupt register 3 (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 8.2.2 FEC status register 6 (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 8.2.3 Measured Signal-to-Noise-Ratio registers 9 - 10 (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 8.2.4 Viterbi error count at Viterbi input registers 11 - 13 (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 8.2.5 Reed-Solomon bit errors corrected registers 14 - 16 (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8.2.6 Reed-Solomon uncorrected block errors registers 17 - 18 (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.0 Automatic Gain Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.1 Automatic gain control read/write registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.1.1 AGC control register 39 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.1.2 AGC_REF Reference Value register 41 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.2 Automatic gain control read registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.2.1 Measured signal level at MT312 input register 19 (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.2.2 Measured AGC feed back value registers 108 - 110 (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 10.0 MPEG Packet Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10.1 MPEG clock modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10.1.1 MANUAL MOCLK = 0 and DIS_SR = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10.1.2 MANUAL MOCLK = 0 and DIS_SR = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10.1.3 MANUAL MOCLK = 1 and DIS_SR = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10.1.4 MANUAL MOCLK = 1 and DIS_SR = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 10.2 Data Output Header Format - DVB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.3 MPEG/DSS Data Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
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MT312
Design Manual
10.3.1 ERR_IND = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.3.2 ERR_IND = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 10.4 Data output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 10.5 MPEG Packet Data Output Read/Write Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10.5.1 Output data control register 96 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10.5.2 Monitor Control register 103 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 11.0 Secondary Registers for Test and De-Bugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 11.1 Read/Write Secondary Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 11.2 Secondary Registers for Test and De-Bugging Read/Write Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11.2.1 AGC Initial Value register 40 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11.2.2 AGC Maximum Value register 42 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11.2.3 AGC Minimum Value register 43 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11.2.4 AGC Lock Threshold Value register 44 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11.2.5 AGC Lock Threshold Value register 45 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11.2.6 AGC Power Setting Initial Value register 46 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11.2.7 QPSK Miscellaneous register 47 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11.2.8 SNR_LOW threshold value register 48 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11.2.9 SNR_HIGH threshold value register 49 (R/W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 11.2.10 Timing Synchronisation Sweep Rate register 50 (R/W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 11.2.11 Timing Synchronisation Sweep Limit Low register 51 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 11.2.12 Timing Synchronisation Sweep Limit High register 52 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 11.2.13 Carrier Synchronisation Sweep Rate 1 register 53 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 11.2.14 Carrier Synchronisation Sweep Rate 2 register 54 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 11.2.15 Carrier Synchronisation Sweep Rate 3 register 55 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 11.2.16 Carrier Synchronisation Sweep Rate 4 register 56 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 11.2.17 Carrier Synchronisation Sweep Limit register 57 (R/W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 11.2.18 Timing Synchronisation Coefficients registers 58 - 60 (R/W). . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 11.2.19 Carrier Synchronisation Proportional Part Coefficients registers 61 - 62 (R/W) . . . . . . . . . . . . . 68 11.2.20 Carrier Synchronisation Integral Coefficients registers 63 - 64 (R/W) . . . . . . . . . . . . . . . . . . . . . 69 11.2.21 QPSK Output Scale Factor register 65 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 11.2.22 Timing Lock Detect Threshold out of lock register 66 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 11.2.23 Timing Lock Detect Threshold in lock register 67 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 11.2.24 Frequency Lock Detect Threshold register 68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 11.2.25 Phase Lock Detect Threshold out of lock registers 69 - 72 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . 70 11.2.26 Phase Lock Detect Threshold in lock registers 73 - 76 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 11.2.27 Phase Lock Detect Accumulator Time register 77 (R/W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 11.2.28 Sweep PAR register 78 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 11.2.29 Start up Time register 79 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 11.2.30 Loss Lock Threshold register 80 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 11.2.31 FEC Lock Time register 81 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 11.2.32 Loss Lock Time register 82 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 11.2.33 Viterbi Error Period registers 83 - 85 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 11.2.34 Viterbi Set up register 86 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 11.2.35 Viterbi Reference Byte 0 register 87 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 11.2.36 Viterbi Reference Byte 1 register 88 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 11.2.37 Viterbi Reference Byte 2 register 89 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 11.2.38 Viterbi Reference Byte 3 register 90 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 11.2.39 Viterbi Reference Byte 4 register 91 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 11.2.40 Viterbi Reference Byte 5 register 92 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 11.2.41 Viterbi Reference Byte 6 register 93 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 11.2.42 Viterbi Maximum Error register 94 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 11.2.43 Byte Align Set up register 95 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 11.2.44 Program Synchronising Byte register 98 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 11.2.45 AFC Frequency Search Threshold register 99 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
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11.2.46 Accumulator Differential Threshold register 100 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 11.2.47 QPSK Lock Control register 101 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 11.2.48 QPSK State Control register 102 (R/W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 11.2.49 QPSK Reset register 104 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 11.2.50 QPSK Test Control register 105 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 11.2.51 QPSK Test State register 106 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 11.2.52 Test Mode register 125 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 11.3 Read only Secondary Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 11.4 Secondary Registers for Test and De-Bugging Read Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 11.4.1 Test Read register 107 (R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 12.0 Microprocessor Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 12.1 Primary 2-wire Bus Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 12.2 RADD: 2-wire Register Address (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 12.3 Primary 2-wire Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 12.4 Secondary 2-wire bus for tuner control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 12.5 Examples of 2-wire Bus Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 12.6 Primary 2-wire Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 13.0 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 13.1 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 13.2 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 13.3 Crystal Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 13.4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 13.5 MT312 Pinout Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 13.6 Alphabetical Listing of Pin-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 14.0 MT312 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 14.1 Read/Write Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 14.2 Read Only Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 15.0 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
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MT312 List of Figures
Design Manual
Figure 1 - MT312 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 2 - Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 3 - Viterbi block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 4 - Viterbi error count measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 5 - Viterbi error count coarse indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 6 - DVB conceptual diagram of the convolutional de-interleaver block. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7 - DSS conceptual diagram of the convolutional de-interleaver block. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 8 - DVB Block Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 9 - DVB energy dispersal conceptual diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 10 - DVB energy dispersal conceptual diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 11 - MT312 control structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 12 - MT312 Power-up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 13 - Initialization sequence in DVB mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 14 - Simple channel change sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 15 - Channel change sequence with new symbol rate, DVB mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 16 - Channel change sequence with search mode, DVB mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 17 - Results of symbol rate and code rate search, DVB or DSS mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 18 - A DiSEqCTM data byte interrupting a continuous 22kHz tone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 19 - One DiSEqCTM data byte - 0x11 (hex) plus parity bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 20 - DVB Transport Packet Header Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 21 - BKERR example when ERR_IND is low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 22 - BKERR example when ERR_IND is high. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure 23 - MT312 Data Output Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Figure 24 - Primary 2-wire Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Figure 25 - Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
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MT312 List of Tables
Design Manual
Table 1 - MT312 register map overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 2 - Register usage overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 3 - Symbol Sweep Ranges for General Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 4 - Symbol Sweep Ranges for 90MHz System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 5 - Viterbi Code Rate Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 6 - Sigma Delta Clock Decimation Ratio Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 7 - MPEG Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 8 - MOCLK Input Minimum And Maximum Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 9 - Read/write Secondary Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 10 - Viterbi Code Rate Search Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 11 - Primary 2-wire bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
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MT312
Overview
Design Manual
The MT312 is a QPSK/BPSK 1 to 45MS/s demodulator and channel decoder for digital satellite television transmissions compliant to both DVB-S and DSS standards and other systems, such as LMDS, that use the same architecture. A Command Driven Control (CDC) system is provided making the MT312 very simple to program. After the tuner has been programmed to the required frequency to acquire a DVB transmission, the MT312 requires a minimum of five registers to be written. The MT312 provides a monitor of bit error rate after the QPSK module and also after the Viterbi module. For receiver installation, a high speed scan or 'blind search' mode is available. This allows all signals from a given satellite to be evaluated for frequency, symbol rate and convolutional coding scheme. The phase of the IQ signals can be automatically determined. Full DiSEqCTM v2.2 is provided for both writing and reading DiSEqCTM messages. Storage in registers for up to eight data bytes sent and eight data bytes received is provided.
MPEG/ DSS Packets
I I/P Dual ADC Q I/P De-rotator Decimation Filtering Timing recovery Matched filter Phase recovery DVB DSS FEC
Analog AGC Ccontrol
Clock Generation
Acquisition Control
2-wire Bus Interface
Bus I/O
Figure 1 - MT312 functional block diagram Additional Features * 2-wire bus microprocessor interface. * All-digital clock and carrier recovery. * On-chip PLL clock generation using a low cost 10 to 15MHz crystal. * 3.3V operation. * 80 pin MQFP package. * Low external component count. * Commercial temperature range 0 to 70C. Demodulator * BPSK or QPSK programmable. * Optional fast acquisition mode for low symbol rates. Viterbi * Programmable decoder rates 1/2, 2/3, 3/4, 5/6, 6/7, 7/8. * Automatic spectrum resolution of IQ phase. * Constraint length k=7. * Trace back depth 128. * Extensive SNR and BER monitors. De-Interleaver * Compliant with DVB and DSS standards. Reed-Solomon * (204, 188) for DVB and (146,130) for DSS. * Reed-Solomon bit-error-rate monitor to indicate Viterbi performance. De-Scrambler * EBU specification de-scrambler for DVB mode. Outputs * MPEG transport parallel & serial output. * MPEG clock input for external synchronising of MPEG data output. * Integrated MPEG2 TEI bit processing for DVB only. Application Support * Channel decoder system evaluation board. * Windows based evaluation software. * ANSI-C generic software.
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Zarlink Semiconductor Inc.
MT312
1.0 Application Diagram
Design Manual
Figure 2 - Application schematic
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Zarlink Semiconductor Inc.
MT312
2.0
2.1
Design Manual
Functional Overview
Introduction
MT312 is a single-chip variable rate digital QPSK/BPSK satellite demodulator and channel decoder. The MT312 accepts baseband in-phase and quadrature analogue signals and delivers an MPEG or DSS packet data stream. Digital filtering in MT312 removes the need for programmable external anti-alias filtering for all symbol rates from 1 to 45MS/s. Frequency, timing and carrier phase recovery are all digital and the only feedback to the analogue front-end is for automatic gain control. The digital phase-recovery loop enables very fine bandwidth control that is needed to overcome performance degradation due to phase and thermal noise. All acquisition algorithms are built into the MT312 controller. The MT312 can be operated in a Command Driven Control (CDC) mode by specifying the symbol rate and Viterbi code rate. There is also a provision for a search for unknown symbol rates and Viterbi code rates.
2.2
Analogue-to-Digital converter
The MT312 contains dual 6-bit A/D converters which each sample a 500mVpp single-ended analogue input at up to 91MHz. The fixed rate sampling clock is provided on-chip using a programmable PLL needing only a low cost 10 to 15MHz crystal. Different crystal frequencies can be combined with different PLL ratios, depending on the maximum symbol rate, allowing a flexible approach to clock generation.
2.3
QPSK demodulator
The demodulator in the MT312 consists of signal amplitude offset compensation, frequency offset compensation, decimation filtering, carrier recovery, symbol recovery and matched filtering. The decimation filters give continuous operation from 2Mbits/s to 90Mbits/s allowing one receiver to cover the needs of the consumer market as well as the single carrier per channel (SCPC) market with the same components without compromising performance, that is, the channel reception is within 0.5dB from theory. For a given symbol rate, control algorithms on the chip detect the number of decimation stages needed and switch them in automatically. The frequency offset compensation circuitry is capable of tracking out up to 15MHz frequency offset. This allows the system to cope with relatively large frequency uncertainties introduced by the Low Noise Block (LNB). Full control of the LNB is provided by the DiSEqCTM outputs from the MT312. Horizontal/vertical polarisation and an instruction modulated 22kHz signal are available under register control. All DiSEqCTMv2.2 functions are implemented on the MT312. An internal state machine that handles all the demodulator functions controls the signal tracking and acquisition. Various preset modes are available as well as blind acquisition where the receiver has no prior knowledge of the received signal. Fast acquisition algorithms have been provided for low symbol rate applications. Full interactive control of the acquisition function is possible for debug purposes. In the event of a signal fade or a cycle slip, the QPSK demodulator allows sufficient time for the FEC to reacquire lock, for example, via a phase rotation in the Viterbi decoder. This is to minimise the loss of signal due to the signal fade. Only if the FEC fails to re-acquire lock for a long period (which is programmable) the QPSK will try to re-acquire the signal. The matched filter is a root-raised-cosine filter with either 0.20 or 0.35 roll-off, compliant with DSS and DVB standards. Although not a part of the DVB standard, MT312 allows a roll-off of 0.20 to be used with other DVB parameters. An AGC signal is provided to control the signal levels in the tuner section of the receiver and ensure the signal level fed to the MT312 is set at an optimal value under all reception conditions. The MT312 provides comprehensive information on the input signal and the state of the various parts of the device. This information includes Signal to Noise Ratio (SNR), signal level, AGC lock, timing and carrier lock signals. A maskable interrupt output is available to inform the host controller when events occur.
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2.4 Forward error correction
Design Manual
The MT312 contains FEC blocks to enable error correction for DVB-S and DSS transmissions. The Viterbi decoder block can decode the convolutional code with rates 1/2, 2/3, 3/4, 5/6, 6/7 or 7/8. The block features automatic synchronisation, automatic IQ phase resolution and automatic code rate detection. The trace back depth of 128 provides better performance at high code rates and the built-in synchronisation algorithm allows the Viterbi decoder to lock onto signals with very poor signal-to-noise ratios. A Viterbi bit error rate monitor provides an indication of the error rate at the QPSK output. The 24-bit error count register in the Viterbi decoder allows the bit error rate at the output of the QPSK demodulator to be monitored. The 24-bit bit error count register in the Reed-Solomon decoder allows the Viterbi output bit error rate to be monitored. The 16-bit uncorrectable packet counter yields information about the output packet error rate. These three monitors and the QPSK SNR register allow the performance of the device and its individual components, such as the QPSK demodulator and the Viterbi decoder, to be monitored extensively by the external microprocessor. The frame/byte align block features a sophisticated synchronisation algorithm to ensure reliable recovery of DVB and DSS framed data streams under worst case signal conditions. The de-interleaver uses on-chip RAM and is compatible with the DVB and DSS algorithms. The Reed-Solomon decoder is a truncated version of the (255, 239) code. The code block size is 204 for DVB and 146 for DSS. The decoder provides a count of the number of uncorrectable blocks as well as the number of bit errors corrected. The latter gives an indication of the bit error rate at the output of the Viterbi decoder. In DVB mode, spectrum de-scrambling is performed compatible with the DVB specification. The final output is a parallel or serial transport data stream, packet sync, data clock, and a block error signal. The data clock may be inverted under software control.
2.4.1
Viterbi error count measurement
A method of estimating the bit error rate at the output of the QPSK block has been provided in the Viterbi decoder. The incoming data bit stream is delayed and compared with the re-encoded and punctured version of the decoded bit stream to obtain a count of errors, see Figure 3. The measurement system has a programmable register to determine the number of data bits (the error count period) over which the count is being recorded. A read register indicates the error count result and an interrupt can be generated to inform the host microprocessor that a new count is available. The VIT_ERRPER_H-M-L group of three registers is programmed with the required number of data bits (the error count period) (VIT_ERRPER[23:0]). The actual value is four times VIT_ERRPER[23:0]. The count of errors found during this period is loaded by the MT312 into the VIT_ERRCNT_H-M-L trio of registers when the bit count VIT_ERRPER[23:0] is reached. At the same time an interrupt is generated on the IRQ line. Setting the IE_FEC[2] bit in the IE_FEC register enables the interrupt. Reading the register does not clear VIT_ERRCNT [23:0], it is only loaded with the error count.
Viterbi Decoder
Data Bit Stream
Viterbi Encoder
Delay
Comp
Error Count
Figure 3 - Viterbi block diagram
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Error Count VIT_ERRCNT[23:0]
0 0 VIT_ERRPER[23:0] Data Bits
IRQ
Figure 4 - Viterbi error count measurement Figure 4 shows the bit errors rising until the maximum programmed value of VIT_ERRPER[23:0] is reached, when an interrupt is generated on the IRQ line to advise the host microprocessor that a new value of bit error count has been loaded into the VIT_ERRCNT [23:0] register. The IRQ line will go high when the IE_FEC register is read by the host microprocessor. The error count may be expressed as a ratio: VIT_ERRCNT[23:0] VIT_ERRPER[23:0]*4
2.4.1.1
Viterbi error count coarse indication
To assist in the process of aligning the receiver dish aerial, a coarse indication of the number of bit errors being received can be provided by monitoring the STATUS line with the following set up conditions. The frequency of the output waveform will be a function of the bit error count (triggering the maximum value programmed into the VIT_MAXERR[7:0] register and the dish alignment on the satellite. This VIT_MAXERR mode is enabled by setting the FEC_STAT_EN register bit-0. Figure 5 below shows the bit errors rising to the maximum value programmed and triggering a change of state on the STATUS line.
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VITERBI Coarse Bit Error Count
VIT_MAXERR[7:0]
0 0 Data Bits
Status
Figure 5 - Viterbi error count coarse indication
2.4.2
The frame alignment block
The frame alignment algorithm detects a sequence of correctly spaced synchronising bytes in the Viterbi decoded bit-stream and arranges the input into blocks of data bytes. Each block consists of 204 bytes for DVB and 147 bytes for DSS. In the DSS mode, the synchronising byte is removed from the data stream, so only 146 bytes of a block are passed to the next stage. The frame alignment block also removes the 180 phase ambiguity not removed by the Viterbi decoder.
2.4.3 2.4.3.1
The De-interleaver block DVB
Before transmission, the data bytes are interleaved with each other in a cyclic pattern of twelve. This ensures the bytes are spaced out to avoid the possibility of a noise spike corrupting a group of consecutive message bytes. Figure 6 below shows conceptually how the convolutional de-interleaving system works. The synchronisation byte is always loaded into the First-In-First-Out (FIFO) memory in branch 0. The switch is operated at regular byte intervals to insert successively received bytes into successive branches. After 12 bytes have been received, byte 13 is written next to the synchronisation byte in branch 0, etc. In the MT312, this de-interleaving function is realised using on-chip Random Access Memory (RAM).
2.4.3.2
DSS
Before transmission, the data bytes are interleaved with each other in a cyclic pattern of thirteen. This ensures the bytes are spaced out to avoid the possibility of a noise spike corrupting a group of consecutive message bytes. Figure 7 below shows conceptually how the convolutional de-interleaving system works. On the MT312, this function is realised in the same Random Access Memory (RAM) as used for DVB, but utilising a different addressing algorithm.
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Sync word route 0 One byte per position 1 2 3 4 5 6 17x5 bytes 7 8 9 10 11 17x4 bytes 17x3 bytes 17x2 bytes 17x1 7 8 9 10 11 17x11 bytes 17x10 bytes 17x9 bytes 17x8 bytes 17x7 bytes 17x6 bytes 3 4 5 6 0 1 2
Design Manual
Figure 6 - DVB conceptual diagram of the convolutional de-interleaver block
Output
145 0 2 Input 1
12D
12D
12D
Figure 7 - DSS conceptual diagram of the convolutional de-interleaver block
2.4.4
The Reed-Solomon decoder block
DVB and DSS data are encoded using shortened versions of the Reed-Solomon code of block length 255, containing 239 message bytes and 16 check bytes, that is (255,239) with T = 8. Both encoders use the same generator polynomial. The code block size for DVB is 204 and that for DSS is 146. Hence DVB code is (204, 188) and DSS code is (146, 130), with both having T = 8. The block structure of the DVB and DSS Reed-Solomon codes are as shown in Figure 8 and Figure 9 below. The Reed-Solomon decoder can correct up to eight byte errors per packet. If there are more than eight bytes containing errors, the packet is flagged as uncorrectable using the pin BKERR. In the case of DVB the Transport Error Indicator (TEI) bit of the MPEG packet is set to 1, if setting of TEI is enabled.
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2.4.5 The energy dispersal (de-scrambler) block, DVB only
Design Manual
Before Reed-Solomon encoding in the DVB transmission system, the MPEG2 data stream is randomised using the configuration shown in Figure 10 below. This is a Pseudo Random Binary Sequence (PRBS) generator, with the polynomial: 1 + X14 + X15 The PRBS registers are loaded with the initialization sequence as shown, at the start of the first transport packet in a group of eight packets. This point is indicated by the inverted sync byte B8hex (the normal DVB sync byte is 47hex). The data starting with the first byte after the sync byte are randomised by exclusive-ORing data bits with the PRBS (the sync bytes themselves are not randomised). In the decoder, the process of de-randomising or de-scrambling the data is exactly the same as described above. The de-scrambler also inverts the sync byte B8hex so that all MPEG output packets have the same sync byte 47hex.
Sync byte
187 bytes Reed-Solomon encoded block
16 check bytes
Sync byte
187 bytes MPEG transport packet
Figure 8 - DVB Block Structure
130 bytes Reed-Solomon encoded block 130 bytes DSS transport packet
16 check bytes
Figure 9 - DVB energy dispersal conceptual diagram
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Initialization sequence 1 1 0 2 0 3 1 4 0 5 1 6 0 7 1 8 0 9 0 10 0 11 0 12 0 13 0 14
Design Manual
0 15
XOR
Figure 10 - DVB energy dispersal conceptual diagram
2.4.6
Output stage
The transport stream can be output in a byte-parallel or bit-serial mode. The output interface consists of an 8-bit output, output clock, a packet validation level, a packet start pulse and a block error indicator. The output clock rate depends on the symbol rate, QPSK/BPSK choice, convolutional (Viterbi) coding rate, DVB/DSS choice and byte-parallel or bit-serial output mode. This rate is computed by MT312 to be very close to the minimum required to output packet data without packet overlap. Furthermore, the packets at the output of MT312 are as evenly spaced as possible to minimise packet position movement in the transport layer. The maximum movement in the packet synchronisation byte position is limited to 1 output clock period. An external MPEG clock can be input to synchronise the MPEG data output to MPEG decoders.
2.5
Control
Automatic symbol rate search, code rate search, signal acquisition and signal tracking algorithms are built into the MT312 using a sophisticated on-chip controller. The software interaction with the device is via a simple Command Driven Control (CDC) interface. This CDC maps high level inputs such as symbol rates in MS/s and frequencies in MHz, to low level on-chip register settings. The on-chip control state machine and the CDC significantly reduces the software overhead as well as the channel search times. There is also an option for the host processor to by-pass both the CDC as well as the on-chip controller and take direct control of the QPSK demodulator. Once the MT312 has locked to the signal, any frequency offset can be read from the LNB_FREQ error registers 7 and 8. The frequency synthesiser under the software control can be re-tuned in frequency to optimise the received signal within the SAW bandwidth. Note that MT312 compensates for any frequency offsets before QPSK demodulation. Hence a frequency offset will not necessarily lead to a performance loss. Performance loss will occur only if a significant part of the signal is cut off by the base-band filter, due to this frequency offset. This will happen only if the symbol rate is close to the maximum supported by that filter. In such an event it is recommended that front-end be re-tuned to neutralise this error before the filter. It is then necessary for the MT312 to re-acquire the signal. The MT312 can generate control signals to enable full control of the dish and LNB. The chip implements the signals needed for the full DiSEqCTM v2.2 specification. This includes high/low band selection, polarisation and dish position. In this mode, the symbol rate in MS/s and Viterbi code rate are the only values needed to start the MT312 searching for the signal. The CDC module maps the high level parameters into the various low level register settings needed to acquire and track the signal. The low level registers may be read and directly modified to suit very specific requirements. However, this is not recommended.
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High level input/output (MS/s, MHz)
Command Driven Control
MT312 format registers
Acquisition/ Track State Machine
QPSK
Low level register read/write Figure 11 - MT312 control structure
2.5.1
Symbol Rate and Code Rate Search Mode
Where the symbol rate and/or the Viterbi code rate are unknown, the MT312 can be programmed to search for QPSK/BPSK signals. The user should define the range(s) over which the search is required. The MT312 will then locate and track any signal detected. Failure to find a QPSK signal in the specified frequency and specified symbol rate ranges will be indicated by interrupts (see section 7.2 "QPSK Demodulator Read Registers" on page 45). MT312 will carry on searching these ranges after issuing these interrupts. When the MT312 has locked onto a signal, the symbol rate in MS/s may be read from the MONITOR registers. The Viterbi code rate may be read from the FEC_STATUS register. This search facility is primarily for the initial installation of a set top box.
2.6
DiSEqCTM Transmit and Receive Messages
The MT312 has the capability to send and receive DiSEqCTM messages. Eight registers are provided to store a message for transmission and a further eight registers are provided to store a received message. The received bytes have a parity bit and a parity error bit in addition to the eight data bits. These additional bits are read out in sequence following the data bits, so two byte reads are required for each data byte.
2.6.1
DiSEqCTM transmitting messages
The sequence of events to send a message are as follows: 1. Load the required message bytes into the DiSEqCTM instruction register 36, see page 34. Sequential writes to the same register are achieved by setting the Inhibit Auto Incrementing (IAI) bit 7 in RADD, the register address byte. 2. Load the number of bytes (less one) in the DiSEqCTM instruction in the register DISEQC_MODE[5:3], see page 33. 3. Set DISEQC_MODE[2:0] = 4 to command the MT312 to encode the data and transmit the message. 4. Reset DISEQC_MODE[2:0] to either 0 or 1 depending on previous setting of 22kHz off or on. The data loaded into the DISEQC_INSTR register is retained, so that if the same message is to be repeated, stage 1 above can be omitted.
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2.6.2 DiSEqCTM receiving messages
Design Manual
The MT312 will automatically listen for DiSEqCTM messages 5ms after a message has been transmitted. If a return message is expected, the DISEQC_MODE[2:0] must be set to zero in order to leave the LNB control signal free for another DiSEqCTM transmitter to respond. The sequence of events to receive a message are as follows: 1. Enable DISEQC2/GPP2 pin 46 as an input by setting GPP_CTRL register address-20 bit-5 to zero. 2. Enable interrupts if the IRQ pin is being used to interrupt the host processor in DISEQC2_CTRL1 register 121. 3. Monitor DISEQC2_INT register. 4. If bit-3 = 1 and bit-1 = 0, there has been no message received. 5. If a message has been received, bit-0 will be set. If bit-1 is also set the message is complete. DISEQC2_INT register bits-7-4 indicate how many bytes have been received. 6. Read the received message from DISEQC2_FIFO register 120 by setting the Inhibit Auto Incrementing (IAI) bit-7 in RADD, the register address byte and sequentially reading DISEQC2_FIFO for the indicated number of bytes. Each data byte read requires two 2-wire bus reads. The second or the pair of bytes contains the parity bit and a parity bit error indicator. The user may choose to wait for the end of message indication, before reading the message, if it is known that the message is not greater than eight bytes. However, if the length of message is not known, the message should be read out of the FIFO by the host as it is being received. Care must be taken to avoid a FIFO buffer overflow. DISEQC2_INT register bits-7-4 will indicate how many bytes remain in the FIFO.
3.0
MT312 software control
This section describes the sequences of register operations needed to acquire DVB and DSS channels with known or unknown parameters. Communication with the MT312 is via a standard 2-wire bus and the first byte following the chip address, in write mode, is the register address (RADD). The register map is organised to group important read registers at the lowest addresses, then the main control write registers in the next block of addresses. The first register to be written must be the configuration register, which has been placed at the highest register address, because it is only written once during the initialization sequence. The CONFIG register can only be reset by the hardware reset. The MT312 is held in a power saving mode following the hardware reset. After a hardware reset, the MT312 must be taken out of the power save mode by writing a one to the MSB of the CONFIG register (see "The configuration register (127)" on page 21). When MT312 is not being used it can be put back into the power save mode by writing a zero to the MSB of CONFIG.
3.1
MT312 register map overview
.
Address 00 - 06 07 - 19, 108 - 117, 123, 124 20 - 39, 41, 96, 103 40, 42 - 49, 50 - 106, 125 107, 118 - 122 126 127
Description Interrupt and Status Primary signal monitors Primary control parameters Secondary parameters Secondary monitors Chip identification Chip configuration Table 1 - MT312 register map overview
Type read read write/read write/read read read write/read
All write/read registers take on default values on full software reset, except for the configuration register (127), which is only reset to the default value by a hardware reset.
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3.2 Register usage overview
Register Addresses 21, 127, 34, 126 20, 37, 38, 7-8, 111-115 22, 35-36, 121-122, 118-120 23-30, 32, 0-2, 4-5, 116-117, 123-124 31, 33, 97, 3, 6, 9-18 39, 41, 19, 108-110 93, 103 Table 2 - Register usage overview Starting Page 20 25 32 39 49 54 56
Design Manual
Section Title 4.0 MT312 Initialization 5.0 Tuner Control 6.0 DiSEqC Control 7.0 QPSK demodulator 8.0 Forward Error Correction 9.0 Automatic Gain Control 10.0 MPEG Packet Data Output
4.0
4.1
MT312 Initialization
Initialization sequence
MT312 will be in the power save mode after a hardware reset. The first command to be written must be to the CONFIGURATION register at address 127. After loading this register, wait 150s before writing to the RESET register. During this wait, the tuner can programmed to the required channel frequency via the General Purpose Port (register 20). Note that the GPP register occupies the address space before the RESET register. If the AGC slope control bit of AGC_CTRL(39) or the AGC_REF(41) are to be changed, it is best to write to these registers after writing to the RESET register. This will allow the front-end AGC loop to settle while the other registers are being written. Next write 128 to the RESET register (21) to reset the MT312 state machine and all parameter registers to the default settings. It is then necessary to change the default setting of register 49 (see 11.2.9, SNR_HIGH threshold value register 49 (R/W)) to 50 (decimal). If necessary, other default parameters may need to be changed. These may include: * * * * * Slope of AGC control signal - See AGC control register 39 (R/W) [bit-0] AGC_SL bit AGC Reference value - See AGC_REF Reference Value register 41 (R/W) Relative phase the of IQ spectrum - See Viterbi mode register 25 (R/W) [bit-6] LNB frequency search range, default 6MHz See FR_LIM frequency limit register 37 (R/W) For low Baud rates only, set fast frequency acquisition mode - See QPSK control register 26 (R/W) [bit-2] = 1
To invert MOCLK or BKERR output signals - See Output data control register 96 (R/W) After this, the LNB controls are defined, in the DISEQC mode control register 22 (R/W). The signal parameters should then be written to the MT312. The symbol rate (Symbol rate registers 23 - 24 (R/W)) may be specified within 2% of the required value, absolute precision is not required to achieve successful lock and tracking. If the symbol rate is unknown, a search mode is available. Selecting the correct bit of Viterbi mode register 25 (R/W), if known, programs the convolutional code rate. If the code rate is unknown, some or all of the bits of VIT_MODE may be set to force a search for the code rate. Finally, the MT312 is given a GO command, register (27) GO =1, to release the state machine and to start the signal acquisition sequence. This is summarised as an example in Figure 13 Initialization sequence in DVB mode.
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4.2 The configuration register (127)
Design Manual
CONFIG[bits 7-0]: This register is for setting up the MT312. It must be loaded first before any other register. It can only be reset to the default value by the RESET pin being pulled low. CONFIG[bit-7]: 312_EN High = MT312 enable. Low = MT312 disable to save power. DSS_A Mode 0 DVB mode 1 DSS mode 1 - code rate 2/3 0 DSS mode 2 - code rate 6/7 1 DSS Code Rate search
CONFIG[bits 6-5]: DSS_B 0 0 1 1
If both DSS_A and DSS_B are set high, the MT312 will search for the code rate in DSS mode. If either of the DSS_A or DSS_B are set high, the symbol rate is automatically set to 20MS/s and SYM_RATE registers (23 & 24) are ignored. The matched filter root-raised-cosine roll-off is set to 0.20 and bit-0 of QPSK_CTRL (26) is ignored. Also, any code rate programmed into VIT_MODE register (25) and VIT_SETUP register (86) will be ignored. Also in DSS mode, the TS_SW_RATE register (50) must be set to 20, see "Timing Synchronisation Sweep Rate register 50 (R/W)" on page 67. CONFIG[bit-4]: CONFIG[bits3-2]: BPSK High = BPSK Low = QPSK PLL_FACTOR[1:0]: bit-3 bit-2 Multiplication factor 0 0 3 0 1 4 1 0 6 1 1 9 CRYS15 High = 15MHz crystal. Low = 10MHz crystal. ADCEXT High = ADC external. Low = ADC internal.
CONFIG[bit-1]: CONFIG[bit-0]:
e.g. For a crystal frequency of 10MHz, a system clock frequency of 60MHz, the PLL ratio will be 6, requiring the PLL_FACTOR[1:0] = 2. For QPSK reception and ADC internal, the MT312 is enabled by writing 88hex to register 127. MT312 computes the System clock frequency using bit-3 to bit-1 above. This frequency is used internally for computing parameters needed for acquiring the QPSK signal. It is possible to use a crystal frequency other than 10 or 15 MHz. As an example, if the crystal frequency is 10.25MHz and the PLL multiplication factor is 6. Then bit-3 is set to 1 and bit-2 to 0. Bit-1 may be given an arbitrary value (0 or 1). The external software must compute the system clock frequency and load this value (multiplied by 2) to the SYS_CLK register (address 34). In the above example, the system clock frequency is 61.5 MHz and hence the value 123 has to be loaded into SYS_CLK register. The QPSK demodulator checks the SYS_CLK register and if this is non-zero, it uses the contents of this as the system clock frequency, for internal calculations mentioned above. If this register is zero (which is the default setting), QPSK demodulator works out the system clock frequency from bits-3- bit-1 of the CONFIG register assuming that the crystal frequency is either 10 or 15 MHz, as defined by bit-1.
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4.3 Power Supplies
Design Manual
To avoid the possibility of destructive latch-up, the CVDD supply must never, at any time during power-up, exceed 0*5V above the VDD supply and must also remain within the absolute maximum ratings, see section 13.2 "Absolute Maximum Ratings" on page 80. In general therefore, the VDD supply should be established ahead of, or simultaneously with the CVDD supply.
VDD CVDD RESET ADDR[7:1] Don't care Osc ~1ms typ. Figure 12 - MT312 Power-up Sequence Don't care
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Design Manual
Enable MT312: Program CONFIG Reg 127 = 140 (8Chex)
Program tuner via GPP in 'pass through mode' open port with Reg 20 = 64 (40hex) send TUNER DATA via 2-wire bus. close port with Reg 20 = 0
Reset MT312 to default register settings Reg21 = 128 (80hex) Set SYS_CLK = 2*Xtal*PLL_RATIO Set DISEQQC_RATIO (if required) Set AGC_SL (if required) Initialise register: reg 49 = 50 (32hex);
DISEQC_MODE e.g. Horizontal with 22kHz on: Reg 22 = 65 (41hex)
Signal input - symbol rate eg 27.5 MS/s: Reg 23 = 27 (1Bhex) DEFAULT state Reg 24 = 128 (80hex) DEFAULT state
Viterbi code rate eg V_IQ swap not set, CR = 3/4: Reg 25 = 4 (4hex)
QPSK control eg DVB: roll-off = 0.35: Reg 26 = 0 DEFAULT state
GO Release Reset state to start signal capture Reg 27 = 1
Figure 13 - Initialization sequence in DVB mode.
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4.4 Spectral inversion
Design Manual
Spectral inversion of the QPSK signal can be caused by the transmitter or the receiver front-end. In the latter case, this could happen due to the way I-Q conversion is carried out or because the I and Q connections are swapped between the I-Q converter and the MT312. If spectral inversion is caused by the receiver front-end, then this must be removed by swapping I and Q (within MT312) before QPSK demodulation, by setting the Q_IQ_SP bit-6 of QPSK control register 26 (R/W) to 1. If no spectral inversion is caused by the receiver front-end design, then bit-6 of QPSK_CTRL should be set to zero. If the transmitted signal is known to be spectrally inverted, then V_IQ_SP bit-6 of the Viterbi mode register 25 (R/W) may be set to 1, or if the spectral inversion status of the transmitted signal is not known, then the AUT_IQ bit-7 of the same register may be set to 1 to allow the MT312 to determine the spectral inversion automatically.
4.5
Read/write registers
Also see "The configuration register (127)" on page 21
4.5.1
Reset register 21 (R/W)
Def hex 00
NAME RESET bit-7: bit-6: bit-5: bit-4: bit-3: bit-2: bit-1: bit-0: * * * *
ADR 21 FR_312 PR_312 FR_QP PR_QP FR_VIT PR_VIT PR_BA PR_DS
bit-7
bit-6
bit-5 FR_QP
bit-4 PR_QP
bit-3 FR_VIT
bit-2 PR_VIT
bit-1 PR_BA
bit-0 PR_DS R/W
FR_312 PR_312
High = Full reset of MT312 device. High = Partial reset of MT312 device. High = Full reset of QPSK block. High = Partial reset of QPSK block. High = Full reset of Viterbi block. High = Partial reset of Viterbi block. High = Partial reset of Byte Align block. High = Partial reset of De-scrambler block.
Writing a one to these register locations generates a reset pulse three crystal clock periods wide. The register automatically resets to zero after use. A full reset resets the registers to their default values. A partial reset does not reset the registers to their default values.
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4.5.2 System clock frequency register 34 (R/W)
ADR 34 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
Design Manual
NAME SYS_CLK
Def hex R/W 00
SYS_CLK[7:0] - System clock frequency x2 in MHz
SYS_CLK[7:0] = System clock frequency * 2 in MHz. If the reference frequency (a crystal or external clock) is other than 10.000MHz or 15.000MHz the SYS_CLK register must be programmed to indicate the system clock frequency to the calculation unit. The maximum system clock frequency allowed is 91MHz. e.g. for a crystal frequency = 10.111MHz, if the PLL multiplication ratio is 9, the system clock frequency = 91MHz and SYS_CLK[7:0] = 182 (B6hex). The system clock frequency is NOT affected by the setting of SYS_CLK[7:0] register. For 10MHz and 15MHz frequencies, the MT312 calculates the system frequency from bits 3-1 in the CONFIG register (see "The configuration register (127)" on page 21) and this register may be left at the default of 00.
4.6 4.6.1
Read registers Identification register 126 (R)
.
NAME ID
ADR 126
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0 R
Def hex 03
ID[7:0] Chip identification.
ID[7:0]: This register provides an identification number related to the MT312 version
5.0
5.1
Tuner Control
Simple channel change sequence
If the MT312 is running, to change channel keeping the same signal conditions, it is only necessary to change the tuner data and possibly the DiSEqCTM data. NO reset is necessary.
5.2
Channel change sequence with a new symbol rate
If the MT312 is running, to change channel and symbol rate but not Viterbi coding rate, change the tuner data and possibly the DiSEqCTM data and symbol rate. NO reset is necessary.
5.3
Channel change sequence with search mode
If the signal parameters are unknown, it is possible to instruct the MT312 to find a digital signal and report the parameters found. Registers 23 and 24 are programmed with the expected range(s) and the search mode bit SYM_RATE[bit-15] is set high. A code rate search is forced by programming more than one bit in VIT_MODE (25) register. The IQ spectrum phase can be automatically determined by setting bit-7 in the Viterbi mode register 25 (R/W). Note: code rate 6/7 is not searched for in DVB mode. If a signal with the specified symbol rate range (or ranges) is not found in the frequency range searched, a QPSK Baud End interrupt (bit-6, QPSK_INT_L (2)) is issued. When the MT312 QPSK section has locked to the signal, this is indicated in register (6) by QPSK_STAT_H[bit-0] = 1. The symbol rate found can be read from registers (123 124) MONITOR, provided the register (103) MON_CTRL = 3. The tolerance of the result is 0.25%. The 14 MSBs
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of this result (discarding two LSBs) may be written as the 14 LSBs of the 16-bit register pair (23 and 24) SYM_RATE in the non-search mode for re-acquisition of the same channel. The FEC is locked to the signal, when byte align lock in FEC_STATUS[bit-2] = 1. The code rate found can then be read from FEC_STATUS[bits 6-4], see section 8.2.2 "FEC status register 6 (R)" on page 51 for details.
Program tuner via GPP in 'pass through mode' open port with Reg 20 = 64 (40hex) send TUNER DATA via 2-wire bus (5 bytes). close port with Reg 20 = 0
DISEQC_MODE eg Vertical with 22kHz on: Reg 22 = 1 (01hex)
GO Re-acquire signal Reg 27 = 1
Figure 14 - Simple channel change sequence
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Program tuner via GPP in 'pass through mode 'open port with Reg 20 = 64 (40hex) send TUNER DATA via 2-wire bus (5 bytes). close port with Reg 20 = 0
DISEQC_MODE eg Horizontal with 22kHz on: Reg 22 = 65 (41hex)
Signal input - symbol rate eg 22.0 MS/s: Reg 23 = 22 (16hex) Reg 24 = 0
Viterbi code rate eg V_IQ swap not set, CR = 5/6: Reg 25 = 8 (8hex)
GO Re-acquire signal Reg 27 = 1
Figure 15 - Channel change sequence with new symbol rate, DVB mode
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Program tuner via GPP in 'pass through mode' open port with Reg 20 = 64 (40hex) send TUNER DATA via 2-wire bus. close port with Reg 20 = 0
DISEQC_MODE eg Horizontal with 22kHz on: Reg 22 = 65 (41hex)
Signal input - Search mode eg for SYS_CLK=60MHz and 30 to 20 MS/s range: Reg 23 = 136 (88hex) Reg 24 = 0
Viterbi code rate search eg set: AUTO IQ detection Reg 25 = 175 (AFhex)
GO Re-acquire signal Reg 27 = 1
Figure 16 - Channel change sequence with search mode, DVB mode
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Program MONITOR to read symbol rate MON_CTRL Reg 103 = 3
Read symbol rate from MONITOR registers 123 & 124. Symbol rate = MONITOR_H_L/1024 MS/s "e.g. if MONITOR_H_L = 0x5820 then the symbol rate = 22560/1024 = 22*03125, i.e. 22.0 MS/s +/-0.25%.
Read code rate from FEC_STATUS[bit-6-4] register 6. eg if FEC_STATUS = 2C hex signal is locked and the code rate = 3/4
Figure 17 - Results of symbol rate and code rate search, DVB or DSS mode
5.4 5.4.1
Tuner Control Read/Write Registers General purpose port control register 20 (R/W)
ADR 20 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 GPP_DIR[2:0] GPP_PIN[2:0] R/W Def hex 20
NAME GPP_CTRL bit-7: bit-6:
Reserved 2W_PAS
Must be set low. High = 2-wire bus pass-through. Low = GPP pin I/O direction set by GPP_DIR[2:0]. bit-5-3: GPP_DIR[2:0] Any bit set high configures the corresponding GPP[2:0] pin as an output Any bit set low configures the corresponding GPP[2:0] pin as an input Mixed use of pins as inputs and outputs is allowed. If bit-6 = 1, pass-through mode, then: GPP_DIR[1:0] are ignored, bit-2: = Input or output set by GPP_DIR[2] - relating to pin 46. Pin 45 = DATA2, this is a transparent, bi-directional connection to the primary DATA1. Pin 44 = CLK2, this is a transparent, bi-directional connection to the primary CLK1.
Reserved. 2W_PAS:
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If bit-6 = 0 then: GPP_DIR[2:0] defines the input/output conditions of the GPP pins and: If a pin[n] is defined as output then: GPP_PIN[n] high forces GPP[n] pin high GPP_PIN[n] low forces GPP[n] pin low If a pin[n] is defined as input then: GPP[n] pin high sets bit GPP_PIN[n] high GPP[n] pin low sets bit GPP_PIN[n] low Allocation of the GPP[2:0] pins is: GPP[2] pin = DiSEqCTM v2.2 input, 3-wire bus enable or can be used for any other application GPP[1] pin = DATA2 or 3-wire bus data GPP[0] pin = CLK2 or 3-wire bus clock The register default state of 20 hex allows the GPP[2] pin to be used for the 3-wire bus enable line and to be kept low at all times, except when programming the synthesiser. When GPP[2] pin is used for DiSEqCTM v2.2 input, the GPP_CTRL register will need to be set to zero after every full reset to make GPP[2] an input.
5.4.2
FR_LIM frequency limit register 37 (R/W)
ADR 37 bit-7 Reserved bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 R/W Def hex 30
NAME FR_LIM
FR_LIM[6:0] - Freq. limit in MHz
bit-7: Reserved. Must be set low. FR_LIM[6:0] frequency search range 125kHz steps (MHz/8). This unsigned 7 bit number represents a search range of +/-0 to +/- 15.875MHz. Default value 30 (hex) = +/- 6.00MHz.
5.4.3
FR_OFF frequency offset register 38 (R/W)
ADR 38 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 R/W Def hex 00
NAME FR_OFF
FR_OFF[7:0] 2's comp. freq. offset in MHz/32
FR_OFF[7:0] Frequency offset correction value in 31.25kHz steps (MHz/32). This 2's complement 8 bit number represents an offset from -4MHz to +3.96875MHz. Default value 0. The frequency search is carried out in the range [(-FR_LIM + FR_OFF), (FR_LIM + FR_OFF)]. The frequency offset register can be useful in reducing the frequency search during channel hopping, especially with low symbol rates. If the location of the wanted channel with respect to the current channel is known and if the synthesiser step size is too large to set the precise frequency of that channel, then the FR_OFF register can be used to take up any residual frequency offset.
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5.5 5.5.1 Tuner Control Read Registers Measured LNB frequency error registers 7 - 8 (R)
ADR 07 08 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 R R
Design Manual
NAME LNB_FREQ H LNB_FREQ L
Def hex 00 00
LNB_FREQ[15:8] Measured LNB frequency error (high byte) LNB_FREQ[7:0] Measured LNB frequency error (low byte)
LNB_FREQ[15:0] Frequency offset in steps of 1*953125kHz (MHz/512). This is a 2's complement 16 bit number. e.g. a hex value of F680 (= -2432) represents an offset of -4.75MHz. Once the chip is in lock, these two registers provide a measurement of the frequency of the signal at the input to MT312. Ideally, this frequency is zero. Due to LNB frequency uncertainty this frequency may take a positive or negative value. The analogue front-end may then be re-tuned to bring this offset close to zero. Note that MT312 indicates the frequency location of the QPSK spectrum with respect to zero frequency. The direction in which the synthesiser frequency has to be stepped depends on the design of the analogue front-end. Also note that in many instances it will not be necessary to re-tune even when there is a relatively large frequency offset. This is because MT312 compensates for this frequency offset before it demodulates the signal. Re-tune only if a substantial part of the QPSK spectrum is affected by the base-band filter which precedes MT312. This will be the case only for symbol rates which are close to the maximum symbol rate supported by the above mentioned filters.
When MT312 locks, part of the frequency offset is taken up by the frequency compensation mixer and part by the carrier synchroniser. LNB_FREQ gives only the value in the frequency compensation mixer. Over a short period of about one second after lock, the carrier synchroniser will transfer all the frequency compensation to the mixer. Hence the LNB_FREQ reading will have an error less than 5% of the symbol rate during this short period after lock. If an accurate frequency reading is needed immediately after lock, the calculation given in section on FREQ_ERR2 has to be performed by external software.
5.5.2
Frequency error 1 and 2 registers 111 - 115 (R)
NAME ADR 111 112 113 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 R R R Def hex 00 00 00
FREQ_ERR1 H FREQ_ERR1 M FREQ_ERR1 L
FREQ_ERR1[23:16] Input frequency error coarse (high byte) FREQ_ERR1[15:8] Input frequency error coarse (middle byte) FREQ_ERR1[7:0] Input frequency error coarse (low byte)
FREQ_ERR1[23:0] is the ratio of frequency compensation mixer offset to system clock x 224. It is a 24-bit signed number. For most purposes the LS byte can be ignored hence the alternative definition is more useful: FREQ_ERR1[23:8] is the ratio of frequency compensation mixer offset to system clock x 216. A 16-bit signed number.
NAME FREQ_ERR2 H FREQ_ERR2 L
ADR 114 115
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0 R R
Def hex 00 00
FREQ_ERR2[15:8] Input frequency error fine (high byte) FREQ_ERR2[7:0] Input frequency error fine (low byte)
FREQ_ERR2 [16:0] is the ratio of carrier synchroniser offset to symbol rate x 28. It is a 16-bit signed number. This value drops to near zero within about a second of signal lock. To obtain an accurate value for the frequency offset at
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any time, especially immediately after lock, the error from each of these registers can be calculated and added together. In practice only the two most significant bytes of FREQ_ERR1 are required, so that the net offset can be calculated as: ERR1 x PLL -----------------------------fOFF = - ---------------------------------- + ERR2 x Rs 65536 262144 Where:
fOFF
= ERR1 = PLL = ERR2 = Rs =
the frequency offset to be applied to the tuner in MHz FREQ_ERR1[23:8] the PLL frequency in MHz FREQ_ERR2[15:0] the symbol rate in MS/s calculated from the value in the "Symbol Rate Output registers 116 - 117 (R)" on page 48
Any frequency error in FREQ_ERR2 transfers to FREQ_ERR1 very rapidly after lock, so that any delay between reading the two values will cause an error in the calculation. It is therefore recommended that the five bytes above are read as a block, especially if the 2-wire bus is subject to congestion or other delays.
6.0
6.1
DiSEqC Control
Screen printouts of DiSEqCTM waveforms
Figure 18 - A DiSEqCTM data byte interrupting a continuous 22kHz tone The timing periods of the 16ms before the data byte and 16ms afterwards to the interrupt being asserted are clearly shown. The restoration of the 22kHz after the interrupt is controlled by software.
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Figure 19 - One DiSEqCTM data byte - 0x11 (hex) plus parity bit
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A 'zero' comprises 22kHz on for 1ms then off for 0.5ms. A 'one' comprises 22kHz on for 0.5ms then off for 1ms. The ninth bit is an odd parity bit.
6.2 6.2.1
DiSEqCTM control read/write registers DISEQC mode control register 22 (R/W)
NAME ADR 22 bit-7 Reserved bit-6 HV bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 R/W Def hex 00
DISEQC_MODE
DISEQC instruction length
22kHz mode
bit-7: bit-6:
Reserved.
Must be set low.
HV H/V polarisation control:
High = Horizontal, DISEQC[1] pin = high Low = Vertical, DISEQC[1] pin = low The DISEQC[1] pin controls the externally generated 13/18V LNB voltage.
bits5-3: bits2-0:
Number of bytes in DiSEqCTM instruction minus 1 to output on the DISEQC[0] pin, i.e. if the message contains four bytes, program bits 5-3 with the value three. DISEQC mode: 0: 1: 2: 3: 4: 5-7: 22kHz off 22kHz on continuous Burst mode - on for 12.5ms = '0' Burst mode - modulated 1:2 for 12.5ms = '1' Modulated with bytes from DISEQC_INSTR Reserved.
Note:
for modes 2 and 3, an interrupt is generated 16ms (see FEC interrupt register 3 (R)) after the '0' or '1' burst. For mode 4, there is a 16ms delay before the message bytes, then an interrupt is generated 16ms after the last message byte has been sent (see FEC interrupt register 3 (R)). The requisite number of bytes must be pre-loaded into the DISEQC instruction register 36 (R/W) before this bit is set, see page 34.
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6.2.2 DISEQC ratio register 35 (R/W)
NAME DISEQC_RATIO ADR 35 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 R/W
Design Manual
Def hex 00
DISEQC_RATIO[7:0]
DISEQC_RATIO[7:0] must be programmed to set the DiSEqCTM output tone frequency. Fout = Fxtal 4*DISEQC_RATIO[7:0]
Where Fout is in kHz and Fxtal is in MHz For a 22kHz output tone, DISEQC_RATIO[7:0] = 11.364 * Fxtal e.g. with Fxtal = 10MHz, DISEQC_RATIO[7:0] = 114, or for 15 MHz 170. For this example, the DISEQC frequency
10 = ------------------ = 21.93kHz 4 x 114
7
For a 10MHz crystal, the tone frequency range is from 9.8kHz with DISEQC_RATIO = 255 to 250kHz with DISEQC_RATIO = 10. A lower value than 10 causes the tone frequency to become unstable, until the DISEQC RATIO = 0, the default, value giving a 22kHz tone frequency. This range is not guaranteed, the maximum tone frequency should be used with caution.
6.2.3
DISEQC instruction register 36 (R/W)
NAME ADR 36 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 R/W Def hex 00
DISEQC_INSTR
DISEQC_INSTR[7:0]
Up to eight instruction data bytes are first loaded into a bank of registers through this register. The 2-wire automatic register address incrementing is turned off during this loading by setting bit-7: IAI = 1 in RADD, (register address). The number of bytes (less one) must be defined in the DiSEqCTM instruction register DISEQC_MODE[5:3]. i.e. DISEQC_MODE[5:3] = (number of bytes in the DiSEqCTM instruction) - 1 When the DiSEqCTM instruction data bytes have been loaded, set DISEQC_MODE[2:0] = 4. At the same time program DISEQC_MODE[5:3] as required. The instruction data bytes are modulated onto the 22kHz signal and output from the DISEQC[0] pin. An interrupt is generated 16ms after all the data bytes have been sent and the MT312 then resets DISEQC_MODE[5:0] to zero, see Figure 18 - "A DiSEqCTM data byte interrupting a continuous 22kHz tone," on page 32.
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6.2.4 DISEQC2 control 1 registers 121 (R/W)
NAME DISEQC2_CTRL1 bits7-6: ADR 121 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
Design Manual
Def hex R/W 00
DISEQC2_CTRL1[7:0]
MIN_TONE_PER
Minimum Tone Period, for controlling (or fine tuning) the DiSEqCTM 2 receive algorithm.
B7-6: 00 01 10 11 bit-5: bit-4:
MIN_TONE_PER 3.0 * DISEQC_RATIO 3.875 * DISEQC_RATIO 3.0 * DISEQC_RATIO 3.75 * DISEQC_RATIO
bit-3: bit-2: bit-1: bit-0:
Send extended pulse to the Status pin 52. This is a test or diagnostics bit. If it is set to 1, then the cleaned up and extended pulse stream is sent to the status pin so that it can be recorded or observed. DISEQC2 reset only the DISEQC2 receive module. Automatically set low again after use. This is the software (partial) reset for DISEQC2 module. If this is set to 1 in the DISEQC2 listen (or receive) period, any listen operations will be aborted and DISEQC2 will wait until the end of the next transmission to expect a reply. Note that the host starting the next DISEQC2 transmission will have a similar effect to writing bit 4. Interrupt enable for bit-3 of DISEQC2_INT STAT register 118. Interrupt enable for bit-2 of DISEQC2_INT STAT register 118. Interrupt enable for bit-1 of DISEQC2_INT STAT register 118. Interrupt enable for bit-0 of DISEQC2_INT STAT register 118. Bits-0 and bit-3 are interrupt enables. These determine whether bits-0 to bit-3 of DISEQC2_INT (register 118, see page 37) have any impact on the pin IRQ 57 of the MT312. Note that buffer overflow interrupt does not have an interrupt enable and hence this cannot be brought out to the IRQ pin.
6.2.5
DISEQC2 Control 2 registers 122 (R/W)
NAME ADR 122 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 R/W Def hex D4
DISEQC2_CTRL2
MIN_PULS_PER
TONE_EXT_PER
MAX_TONE_PER
B[7:5]: MIN_PULS_PER Minimum Pulse Period.
bit-7-5: 000 001 010 011
MIN_PULS_PER 24 * DISEQC_RATIO 25 * DISEQC_RATIO 26 * DISEQC_RATIO 27 * DISEQC_RATIO
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100 101 110 111 B[4-2]: 28 * DISEQC_RATIO 29 * DISEQC_RATIO 30 * DISEQC_RATIO (default) 31 * DISEQC_RATIO TONE_EXT_PER Tone Impulse Extended Period.
Design Manual
bit-1-0: 000 001 010 011 100 101 110 111 B[1-0]:
TONE_EXT_PER 7 * DISEQC_RATIO 8 * DISEQC_RATIO 9 * DISEQC_RATIO 10 * DISEQC_RATIO 11 * DISEQC_RATIO. 12 * DISEQC_RATIO. (default) 13 * DISEQC_RATIO. 14 * DISEQC_RATIO. MAX_TONE_PER Maximum Tone Period.
bit-1-0: 00 01 10 11
TONE_EXT_PER 6.0 * DISEQC_RATIO. (default) 6.25 * DISEQC_RATIO. 5.75 * DISEQC_RATIO. 5.5 * DISEQC_RATIO.
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6.3 6.3.1 DiSEqC Control Read Registers DISEQC2 Interrupt Indicators register 118 (R)
ADR 118 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 R
Design Manual
NAME DISEQC2_INT
Def hex 00
DISEQC2_INT[7:0]
Note that the most significant four bits are not reset on read. The least significant four bits are interrupt bits which are reset when the register is read. Interrupts indicate events in history. The interrupts may be enabled to drive the IRQ pin 57 by setting required bit(s) in the DISEQC2_CTRL1 register 121, see page 35. bit-7-4: Bits-7-4 denote the following number of bytes received: bit-7-4 = (Number of bytes received - Number of bytes read) Hence this is the number of bytes that would be in the FIFO BUFFER if this buffer had unlimited capacity. Since the size of this buffer is only 8 bytes, if the above difference, given by bits 7-4, exceeds eight, that indicates buffer overflow. bit-3: Silent period exceeds 176 ms interrupt (reset on read) The host may enable interrupts bit-1 and bit-3. Then when an interrupt is received, the host may read the DISEQC2_INT register. Then if bit-3 is one and bit-1 is 0, this indicates there has been a continuous period 176ms of silence since the end of the transmission. If the host is expecting a reply, then this silence may be taken to signify a hardware fault in the system. There is a 5-bit number in the DISEQC2_STATUS BYTE which indicates the length of a continuous period of silence up to the read time, in multiples of 16 ms. bit-2: Receive error interrupt (reset on read). Bit-2 indicates an error in the received message. This does not refer to a parity error. It indicates that a bit has been lost due to excessive noise or interference in the return channel. This is identified within MT312 by the occurrence of an excessively long tone or silence period within a byte. bit-1: End of message interrupt (reset on read). Bit-1 indicates a new message has been received. The end of a message is identified by a silent period of about 6 ms following a byte. The end-of-message interrupt bit makes it easier for the host processor to read DiSEqCTM data from MT312. Instead of reading a byte at a time, it can read the message as a whole. It is important to note that MT312 does not stop accepting bytes after setting end-of-message interrupt. It will receive new messages, if any, whilst the current message is being read by the host. Since the 2-wire bus read rate is higher than the byte receive rate, there is no reason for FIFO buffer overflow. After every received message there will be an interrupt. bit-0: End of byte interrupt (reset on read). Bit-0 is set when a new byte is received. The host may wish to ignore byte interrupts and opt to read received messages, as described below. It is important to note that MT312 does not stop accepting bytes after setting end-of-message interrupt. It will receive new messages, if any, whilst the current message is being read by the host. Since 2-wire bus read rate is higher than the byte receive rate, there is no reason for FIFO buffer overflow. After every received message there will be an interrupt.
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6.3.2 DISEQC2 Status Indicators register 119 (R)
NAME DISEQC2_STAT bit-7-5: bit-4-0: ADR 119 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 R
Design Manual
Def hex 00
DISEQC2_STATUS[7:0]
DISEQC2 Finite State Machine State. This is primarily for debugging the device. Silent period since last received bit, in multiples of 16 ms. Bits 4-0 are reset to zero when a bit is received. When this 5-bit number reaches 11 (176ms), the interrupt bit-3 of DISEQC2_INT register is set. This is saturated at 31. Hence if the total period exceeds 496 ms this counter will continue to indicate 31.
6.3.3
DISEQC2 FIFO register 120 (R)
Odd byte read of register 120:
NAME DISEQC2_FIFO
ADR 120
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0 R
Def hex 00
DISEQC2_FIFO[7:0]
Even byte read of register 120: This FIFO contains data bytes and parity bits collected. This can hold a maximum of 8 data bytes, 8 parity bits and 8 parity error bits. The parity error bit is defined as the inverse of the exclusive-OR combination (or modulo-2 addition) of all 9 bits (8 data and 1 parity). This bit will be zero when there is no parity error.
NAME DISEQC2_FIFO
ADR 120
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1 Par error
bit-0 Par bit R
Def hex 00
Reserved
Refer to preceding section for buffer overflow. The received bytes are read from this location with 2-wire bus auto-increment bit set to zero. The received bytes will be available in the order received, i.e. the buffer is a First In First Out (FIFO) memory. Note that two read operations are needed for each byte. The first read operation will give the data byte and the second will provide the associated parity bit (bit-0) and the parity-error bit (bit-1), the other 6 bits will be zero. For example, if four bytes are received, then eight read operations (with auto-increment bit set to zero) are needed to get all data bytes as well as the parity bits. The number of bytes received is given by bits-3-0 of DISEQC2_STATUS BYTES register 119.
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7.0
7.1 7.1.1
Design Manual
QPSK demodulator
QPSK Demodulator Read/Write Registers Symbol rate registers 23 - 24 (R/W)
ADR 23 24 bit 15 = 0 bit 15 = 1 bit-7 SEARCH bit-6 SR_FMT bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 R/W R/W Def hex 1B 80
NAME SYM_RATE_H SYM_RATE_L bit-15:
SYM_RATE[13:8] in MS/s (high byte)
SYM_RATE[7:0] in MS/s (low byte) known symbol rate mode search mode normal mode, bits 13:0 = symbol rate * 256 reserved mode
SEARCH
bit-14:
SR_FMT
bit 14 = 0 bit 14 = 1
Known symbol rate mode: bits13-0: Required symbol rate in MS/s x 256. Unsigned 14-bit number. e.g. for a symbol rate of 27.5 MS/s: SYM_RATE = 27.5 * 256 = 7040 = 1B80 (hex)
If either of the two DSS bits are set in the CONFIG register, then the SYM_RATE register contents are ignored and the symbol rate is taken as 20 MS/s. Hence it is not necessary to program the SYM_RATE register for DSS applications. Search Mode: bits 13-12: don't care bits 11-0: sub-ranges to be searched (scaled by clock rate).
The total symbol rate range is divided into 12 sub-ranges. A bit in the above register pair is assigned to each sub-range, as defined in Figure 3 below. The symbol rate sub-range or sub-ranges to be searched are defined by setting the appropriate bits high. Small overlaps are automatically provided between successive sub-ranges. Note that the lowest sub-ranges have been provided for 90 MHz operation and the device has not been optimised for operation below 1 MS/s. Therefore for example, (with a 90MHz system clock) to search for all signals with symbol rates from 15 MS/s to 45 MS/s, bits 15, 11, 10 & 9 are all set to `1' and all other to `0'.
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Bit 11 10 9 8 7 6 5 4 3 2 1 0 Symbol Rate Sub Range MS/s SYS_CLK/2 to SYS_CLK/3 SYS_CLK/3 to SYS_CLK/4 SYS_CLK/4 to SYS_CLK/6 SYS_CLK/6 to SYS_CLK/8 SYS_CLK/8 to SYS_CLK/12 SYS_CLK/12 to SYS_CLK/16 SYS_CLK/16 to SYS_CLK/24 SYS_CLK/24 to SYS_CLK/32 SYS_CLK/32 to SYS_CLK/48 SYS_CLK/48 to SYS_CLK/64 SYS_CLK/64 to SYS_CLK/96 SYS_CLK/96 to SYS_CLK/128
Design Manual
Table 3 - Symbol Sweep Ranges for General Case Bit 11 10 9 8 7 6 5 4 3 2 1 0 Symbol Rate Sub Range MS/s 45 - 30 30 - 22.5 22.5 - 15 15 - 11.25 11.25 - 7.5 7.5 - 5.625 5.625 - 3.75 3.75 - 2.8125 2.8125 - 1.875 1.875 - 1.40625 1.40625 - 0.9375 0.9375 - 0.703125
Table 4 - Symbol Sweep Ranges for 90MHz System Clock
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7.1.2 Viterbi mode register 25 (R/W)
ADR 25 bit-7 AUT_IQ bit-6 V_IQ_SP bit-5 CR_ 7/8 bit-4 CR_ 6/7 bit-3 CR_ 5/6 bit-2 CR_ 3/4 bit-1 CR_ 2/3 bit-0 CR_ 1/2
Design Manual
NAME VIT_MODE
Def hex R/W 44
bit-7:
AUT_IQ
Automatic IQ phase High = Search for correct IQ phase. Low = Use IQ phase setting in V_IQ_SP.
When this bit is set high, the Viterbi decoder will start with the IQ phase defined in V_IQ_SP and the code rate defined in VIT_MODE[5:0], to establish the correct IQ phase of the incoming signal. When this is established, the V_IQ_SP bit will be set to that phase indication so that it can be read by software for subsequent re-tuning to the same channel. bit-6: V_IQ_SP Swap I and Q inputs to the Viterbi decoder to overcome spectral inversion caused by the transmitter. High = I-Q swap Low = No I-Q swap If the transmitted signal is known to be spectrally inverted then set this bit to 1. When AUT_IQ is set high, this bit will indicate the IQ phase following successful channel acquisition. In manual mode, when AUT_IQ is set low, software is required to determine the spectrum phase and control this bit externally. bit-5: bit-4: bit-3: bit-2: bit-1: bit-0: CR_7/8 CR_6/7 CR_5/6 CR_3/4 CR_2/3 CR_1/2 High = Viterbi code rate 7/8. High = Viterbi code rate 6/7. High = Viterbi code rate 5/6. High = Viterbi code rate 3/4. High = Viterbi code rate 2/3. High = Viterbi code rate 1/2.
The Viterbi decoder will search for a signal with the code rates selected by this register. If one code rate is selected, the MT312 will search for a signal with only that code rate. If the code rate is unknown then all bits 5-0 may be set, allowing the MT312 to search for all code rates. It is also possible to choose the starting point for the code rate search by setting a bit in VIT_SETUP[bit-3:1] register (86). After searching for a signal with the initial code rate, if no signal is found the search proceeds to the next higher code rate, see page 72. All selected code rates are searched until a signal is found, irrespective of the start point. Setting the starting code rate for a search to the most likely value, can speed up a search. In the DSS mode the code rate is not specified using VIT_MODE register. If either of the two DSS bits of the Configuration Register (127) are set, then the code rates selected by the VIT_MODE register are ignored. The DSS code rate selection is carried out as described in section 4.1 "Initialization sequence" on page 20. The result of the search is reported in the FEC_STAT register (6), see page 51.
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7.1.3 QPSK control register 26 (R/W)
Design Manual
NAME QPSK_CTRL
ADR 26
bit-7 Rsvd
bit-6 Q_IQ_SP
bit-5 Rsvd
bit-4 Rsvd
bit-3 Rsvd
bit-2 AFC_M
bit-1 Rsvd
bit-0 ROLL_20 R/W
Def hex 00
bit-7: bit-6:
Rsvd
Must be set low. Swap I and Q inputs before QPSK demodulation to overcome spectral inversion caused by the receiver front-end, for example through the swapping I and Q wires on the board. High = I-Q swap Low = No I-Q swap
Q_IQ_SP
bit-5: bit-4: bit-3: bit-2: bit-1: bit-0:
Reserved Reserved Reserved AFC_M Reserved ROLL_20
Must be set low. Must be set low. Must be set low. High = Use AFC mode, for low symbol rates only, < 10MSym/s. Must be set low. High = Roll-off 0.20 Low = Roll-off 0.35
If either of the two DSS control bits of the Configuration Register (127) is active (section 4.2), then bit-0 (ROLL_20) is ignored and the matched filter root-raised-cosine roll-off factor is taken as 0.20. Hence this bit only allows the choice of roll-off in the DVB mode. If the Q_IQ_SP bit is not set correctly, i.e. according to the hardware in use, the AUT_IQ bit in the VIT_MODE register [see Viterbi mode register 25 (R/W)] will allow the system to lock, but calculated frequency offsets will have the wrong sign, and may confuse the software.
7.1.4
Go command register 27 (R/W)
Def hex R/W 00
NAME GO bit-7-1: bit-0:
ADR 27
bit-7
bit-6
bit-5
bit-4 Reserved
bit-3
bit-2
bit-1
bit-0 GO
Reserved - not used. GO High = release reset state to start signal capture, automatically reset to zero. Low = no action.
If this register is read, it will return zero.
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7.1.5 QPSK interrupt output enable registers 28 - 30 (R/W)
Design Manual
When the bits of these three registers are set high, they enable an event to generate an interrupt on the IRQ pin 57. All interrupts may be enabled together. These registers do not affect the indication of events in the read registers 0 - 3. Def hex R/W 00
NAME IE_QPSK_H bit-7: bit-6: bit-5: bit-4: bit-3: bit-2: bit-1: bit-0:
ADR 28
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
IE_QPSK[23:16] Interrupt enable QPSK (high byte)
High = Enable QPSK_CT_LOCK indication on interrupt pin. High = Enable QPSK_CT_UNLOCK indication on interrupt pin. High = Enable QPSK_LOCK indication on interrupt pin. High = Enable QPSK_UNLOCK indication on interrupt pin. High = Enable QPSK_TS_LOCK indication on interrupt pin. High = Enable QPSK_TS_UNLOCK indication on interrupt pin. High = Enable QPSK_CS_LOCK indication on interrupt pin High = Enable QPSK_CS_UNLOCK indication on interrupt pin. Def hex R/W 00
NAME IE_QPSK_M bit-7: bit-6: bit-5: bit-4: bit-3: bit-2: bit-1: bit-0:
ADR 29
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
IE_QPSK[15:8] Interrupt enable QPSK (middle byte)
High = Enable QPSK_FE_AGC_LOCK indication on interrupt pin. High = Enable QPSK_TS_AGC_LOCK indication on interrupt pin. High = Enable QPSK_TS_AGC_UNLOCK indication on interrupt pin. High = Enable QPSK_FR_LOCK indication on interrupt pin. High = Enable QPSK_FR_UNLOCK indication on interrupt pin. High = Enable QPSK calculation complete indication on interrupt pin. High = Enable QPSK_TS_MAX indication on interrupt pin. High = Enable QPSK_CS_MAX indication on interrupt pin.
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Design Manual
NAME IE_QPSK_L bit-7: bit-6: bit-5: bit-4: bit-3: bit-2: bit-1: bit-0:
ADR 30
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0 R/W
Def hex 00
IE_QPSK[7:0] Interrupt enable QPSK (low byte)
High = Enable QPSK_ST_CHA indication on interrupt pin. High = Enable QPSK frequency end indication on interrupt pin. High = Enable QPSK_BAUD end indication on interrupt pin. High = Enable QPSK_AFC success indication on interrupt pin. High = Enable QPSK_AFC fail indication on interrupt pin. High = Enable QPSK next FRS21 indication on interrupt pin. High = Enable QPSK same FRS21 indication on interrupt pin. High = Enable QPSK LTV limit indication on interrupt pin.
7.1.6
QPSK status output enable register 32 (R/W)
These bits enable various QPSK outputs on the STATUS pin. If more than one bit is enabled then the logical-OR combination of the selected status signals will appear on the STATUS pin (52). Def hex R/W 00
NAME QPSK_STAT_EN bit-7: bit-6: bit-5: bit-4: bit-3: bit-2: bit-1: bit-0:
ADR 32
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
QPSK_STAT_EN[7:0]
High = QPSK_TS sweep on High = QPSK_CS sweep on High = QPSK_FR_LOCK High = QPSK_TS_AGC_LOCK High = QPSK_TS_LOCK High = QPSK_CS_LOCK High = QPSK_CT_LOCK Reserved. Must be set low.
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7.2 7.2.1 QPSK Demodulator Read Registers QPSK Interrupt registers 0 - 2 (R)
Design Manual
The majority of these interrupts are for diagnostic purposes and generally not useful in normal operation, unless otherwise indicated.
NAME QPSK_INT_H bit-7: bit-6: bit-5: bit-4: bit-3: bit-2: bit-1: bit-0:
ADR 00
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0 R
Def hex 00
QPSK_INT[23:16] interrupt QPSK (high byte)
High = QPSK Carrier and Timing LOCK - important indicator. High = QPSK Carrier and Timing UNLOCK High = QPSK_LOCK - important indicator. High = QPSK_UNLOCK High = QPSK Timing LOCK High = QPSK Timing UNLOCK High = QPSK Carrier LOCK High = QPSK Carrier UNLOCK
Reading an interrupt register resets that register. After the QPSK demodulator achieves Carrier and Timing Lock, from now on referred to as QPSK CT Lock, it waits some time for the FEC to confirm this lock. When the FEC locks, the QPSK enters QPSK Lock state. The time QPSK waits for the FEC to gain lock is programmable via register 81 (see Section 11.2.31 "FEC Lock Time register 81 (R/W)" on page 71). If the FEC does not achieve lock during this period (very unlikely), then MT312 drops its QPSK CT Lock status and resumes search for another QPSK signal.
NAME QPSK_INT_M bit-7: bit-6: bit-5: bit-4: bit-3: bit-2: bit-1: bit-0:
ADR 01
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0 R
Def hex 00
QPSK_INT[15:8] Interrupt QPSK (middle byte)
High = QPSK_FE_AGC_LOCK High = QPSK Digital Internal AGC LOCK High = QPSK Digital Internal AGC UNLOCK High = QPSK_FR_LOCK High = QPSK_FR_UNLOCK High = QPSK calculation complete High = QPSK_TS_MAX High = QPSK_CS_MAX
Reading an Interrupt register resets that register.
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NAME QPSK_INT_L ADR 02 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 R
Design Manual
Def hex 00
QPSK_INT[7:0] Interrupt QPSK (low byte)
The majority of these interrupts are for diagnostic purposes and generally not useful in normal operation, unless otherwise indicated. bit-7: bit-6: bit-5: bit-4: bit-3: bit-2: bit-1: bit-0: High = QPSK state change High = QPSK frequency end of search range - important indicator. High = QPSK_BAUD end of range - important indicator. High = QPSK_AFC success High = QPSK_AFC fail High = QPSK next frequency search High = QPSK same frequency search High = QPSK LTV limit
Reading an Interrupt register resets that register. Frequency and symbol rate search is carried out as follows. If the symbol rate is known then MT312 will search the specified frequency range for this symbol rate. Once the end of this range has been reached, "QPSK end of frequency range search" interrupt will be issued and MT312 will resume the search beginning from frequency zero. A "QPSK end of symbol rate range(s) search" interrupt will not be issued. If the symbol rate is not known, then MT312 can be made to search several sub-ranges of symbol rates, by setting up to 12-bits of the pair of SYM_RATE registers, as described in "Symbol rate registers 23 - 24 (R/W)" on page 39. For illustration purposes, assume that the symbol rate sub-ranges SYS_CLK/2 to SYS_CLK/3 and SYS_CLK/4 to SYS_CLK/6 are to be searched. Then MT312 will begin the search from the upper sub-range SYS_CLK/2 to SYS_CLK/3. MT312 will search for a channel with a symbol rate in this range over the specified frequency range, for example 10 MHz. If no channel is found then MT312 will issue a "QPSK end of frequency range search" interrupt and will go on to search the sub-range SYS_CLK/4 to SYS_CLK/6 over the specified frequency range. If no channel is found, then MT312 will issue a "QPSK end of frequency range search" interrupt as well as a "QPSK end of symbol rate range(s) search" interrupt. Then MT312 will return to search the specified frequency range for a symbol rate in the range SYS_CLK/2 to SYS_CLK/3. This process continues indefinitely, unless it is interrupted by host processor software.
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7.2.2 QPSK Status registers 4 - 5 (R)
Design Manual
NAME QPSK_STAT_H bit-15: bit-14: bit-13: bit-12: bit-11: bit-10: bit-9: bit-8:
ADR 04
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0 R
Def hex 00
QPSK_STATUS[15:8] (high byte)
High = QPSK_SNR_MSB High = QPSK_SNR_LSB High = QPSK_FR_LOCK High = QPSK timing AGC lock High = QPSK timing lock High = QPSK carrier lock High = QPSK carrier and timing (CT) lock High = QPSK_LOCK
NAME QPSK STAT L bit-7: bit-6: bit-5-0:
ADR 05
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0 R
Def hex 00
QPSK_STATUS[7:0] (low byte)
High = QPSK Timing sweep on High = QPSK Carrier sweep on Reserved
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Zarlink Semiconductor Inc.
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7.2.3 Symbol Rate Output registers 116 - 117 (R)
Design Manual
NAME SYM_RAT_OP_H SYM_RAT_OP_L
ADR 116 117
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0 R R
Def hex 00 00
SYM_RAT_OP[15:8] Symbol Rate Output (high byte) SYM_RAT_OP[7:0] Symbol Rate Output (low byte)
SYM_RAT_OP[15:0] These two bytes contain a positive number that is inversely proportional to the symbol rate. The decimation ratio index must also be read from the MONITOR register bits B[7:5] and divided by 32 to normalise the result.
- DEC_RATIO PLL_CLK x 8192 Rs = ----------------------------------------------------------- x 2 SYM_RAT_OP + 8192
Where:
Rs = symbol rate in MS/s PLL_CLK = PLL clock frequency in MHz SYM_RAT_OP = value of registers 116 and 117. DEC_RATIO = MONITOR_H[7:5] when MON_CTRL[2:0] = 5.
7.2.4
Monitor registers 123 - 124 (R)
Def hex R R 00 00
NAME MONITOR_H MONITOR_L
ADR 123 124
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
MONITOR[15:8] Monitor (high byte) MONITOR[7:0] Monitor (low byte)
For details, see MON_CTRL register (103) on page 63. MON_CTRL[3:0] = 0: MONITOR_H = CS_SYM_I and MONITOR_L = CS_SYM_Q.
This is a snapshot of two I and Q samples (of the same symbol) after carrier synchroniser. This information can be used to produce a scatter diagram. Keep reading these continuously and mark these as points on a 2-D I-Q plane to get a scatter diagram. MON_CTRL[3:0] = 1: MONITOR_H = DC_OFFSET_I and MONITOR_L = DC_OFFSET_Q.
This will give the amount of DC offset in the I and Q inputs from the ADC compensated by the QPSK. Each of these is a two's complement number. If the 6-bit ADC range is taken to be in the scale -32 to 31, then it is necessary divide DC_OFFSET_I by 16, to bring it to the same scale as the ADC. For example, if we get the DC_OFFSET_I as "11111101", the corresponding two's complement number is -3. However, the actual offset with respect to the ADC scale of [-32, 31] is actually -3/16. The same applies to DC_OFFSET_Q. MON_CTRL[3:0] = 3: MONITOR_H = MS/s OP_H and MONITOR_L = MS/s OP_L.
When the QPSK demodulator is in lock following a symbol rate search, the locked symbol rate may be read from the MONITOR register. Then: Symbol Rate = MONITOR[15:0]/1024. The accuracy of this reading is within 0.25% of the actual symbol rate. Note that the channel with this symbol rate can be subsequently re-acquired without a search by programming the 14 MSBs of the above read-out (discarding the two LSBs) as the 14 LSBs of the 16-bit SYM_RATE register (23,24), see page 39.
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MON_CTRL[3:0] = 5: Decimation ratio = MONITOR[15:13]/32. MON_CTRL[3:0] = 6: M_FLD[7:0]: MONITOR_H = MONITOR_L = M_FLD[7:0].
Design Manual
This byte contains a number calculated in the TS_FLD Timing synchroniser frequency lock detector and is used for frequency lock detection in the manual programming mode. MONITOR_H = M_TLD_H and MONITOR_L = M_TLD_L. Measurement of the Timing lock detector value. Reading the bytes does NOT reset the value. MONITOR_H = M_PLD_H and MONITOR_L = M_PLD_L Measurement of the Phase lock detector value. Reading the bytes does NOT reset the value.
MON_CTRL[3:0] = 7: M_TLD[15:0]: MON_CTRL[3:0] = 8: M_PLD[15:0]:
Other settings of MON_CTRL[3:0] are either reserved for diagnostic purposes or not used.
8.0
8.1 8.1.1
Forward Error Correction
Forward error correction read/write registers FEC interrupt enable register 31 (R/W)
When the bits of this register are set high, they enable an event to generate an interrupt on the pin 57. All interrupts may be enabled together.
NAME IE FEC bit-7: bit-6: bit-5: bit-4: bit-3: bit-2: bit-1: bit-0:
ADR 31
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0 R/W
Def hex 00
IE FEC[7:0] Interrupt enable FEC
High = Enable DiSEqCTM indication on interrupt pin. High = Enable byte align lock lost indication on interrupt pin. High = Enable byte align lock indication on interrupt pin. High = Enable Viterbi lock lost indication on interrupt pin. High = Enable Viterbi lock indication on interrupt pin. High = Enable Viterbi BER monitor period reached indication on interrupt pin. High = Enable de-scrambler lock lost indication on interrupt pin. High = Enable de-scrambler lock indication on interrupt pin.
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8.1.2 FEC_STATUS output enable register 33 (R/W)
Design Manual
If more than one bit is enabled then the logical-OR combination of the selected status signals will appear on the STATUS pin 52. Def hex 14
NAME FEC_STAT_EN bit-7-4: bit-3: bit-2: bit-1: bit-0:
ADR bit-7 bit-6 bit-5 bit-4 33 MOCLK_RATIO[3:0]
bit-3
bit-2
bit-1
bit-0
DS_lock BA_lock VIT_lock BER_tog R/W
MOCLK_RATIO[3:0] MPEG clock ratio - 6. i.e. range is from 6 to 21 see section 10.1.3 "MANUAL MOCLK = 1 and DIS_SR = 0" on page 56. DS_lock BA_lock VIT_lock BER_tog High = De-scrambler lock High = Byte Align lock High = Viterbi lock High = BER toggle. This bit enables an audio frequency signal to be output on the STATUS pin to indicate BER during dish alignment, see section 2.4.1.1 "Viterbi error count coarse indication" on page 13. The frequency of the signal is controlled by VIT_MAXERR register (94), see page 73.
8.1.3
FEC setup register 97 (R/W)
Def hex 03
NAME FEC_SETUP bit-7:
ADR 97
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1 bit-0
DIS_SR ENCL_KO DIS_DS DIS_RS DIS_VIT EN_PRS DS_LK[1:0] R/W
When MANUAL_MOCLK ("Output data control register 96 (R/W)" on page 62) is low then: DIS_SR High = Disable use of symbol rate for MOCLK generation. Low = Use symbol rate for MOCLK generation. When MANUAL MOCLK (register 96 bit 7) is high then: DIS_SR High = Use external MICLK (pin 14) signal for MOCLK. Low = Manually set MOCLK period from MOCLK_RATIO ("FEC_STATUS output enable register 33 (R/W)" on page 50).
bit-6: bit-5: bit-4: bit-3: bit-2: bits1-0:
ENCL_KO DIS_DS DIS_RS DIS_VIT EN_PRS DS_LK[1:0] + 2
High = Enable clock out for test purposes. High = Disable de-scrambler. High = Disable Reed-Solomon decoder. High = Disable Viterbi (Viterbi by pass mode) High = Enable programmed synchronisation byte in register 98 (see "Program Synchronising Byte register 98 (R/W)" on page 74). = Number of bytes for de-scrambler to lose lock. The default register value of 3 is equivalent to 5 bad sync words.
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Zarlink Semiconductor Inc.
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8.2 8.2.1 Forward Error Correction Read Registers FEC interrupt register 3 (R)
Def hex R 00
Design Manual
NAME FEC_INT bit-7: bit-6: bit-5: bit-4: bit-3: bit-2: bit-1: bit-0:
ADR 03
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
FEC_INT[7:0] Interrupt FEC
High = DiSEqCTM event, see "DISEQC instruction register 36 (R/W)" on page 34 High = Byte align lock lost High = Byte align lock - important indicator. High = Viterbi lock lost High = Viterbi lock High = Viterbi BER monitor period reached High = De-scrambler lock lost High = De-scrambler lock
Reading an Interrupt register resets that register.
8.2.2
FEC status register 6 (R)
Def hex R 00
NAME FEC_STATUS bit-7: bit-6-4:
ADR 06
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
FEC_STATUS[7:0]
Reserved Viterbi coding rate bit 6 0 0 0 0 1 1 bit5 0 0 1 1 0 0 bit 4 0 1 0 1 0 1 bits 6-4 0 1 2 3 4 5 Code rate indication 1/2 2/3 3/4 5/6 6/7 7/8
Table 5 - Viterbi Code Rate Indication bit-3: bit-2: bit-1: bit-0: High = De-scrambler lock High = Byte align lock High = Viterbi lock Reserved
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Zarlink Semiconductor Inc.
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8.2.3 Measured Signal-to-Noise-Ratio registers 9 - 10 (R)
Design Manual
NAME M_SNR_H M_SNR_L bit-15:
ADR 09 10
bit-7 Reserved
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0 R R
Def hex 00 00
M_SNR[14:8] measured SNR (high byte) M_SNR[7:0] measured SNR (low byte)
Reserved
M_SNR[14:0]: These two registers provide a indication of the signal to noise ratio of the channel being received by the MT312. It should not be taken as the absolute value of the SNR. 13312 - M_SNR[14:0] dB 683
Eb/N0 ~
The equation given only holds for Es/N0 values in the range 3 to 15 dB, i.e. Eb/N0 values in the range 0 to 12 dB.
8.2.4
Viterbi error count at Viterbi input registers 11 - 13 (R)
Def hex R R 00 00 00
NAME VIT_ERRCNT_H VIT_ERRCNT_M VIT_ERRCNT_L
ADR bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 11 12 13 VIT_ERRCNT[23:16] - Viterbi error count (high byte) VIT_ERRCNT[7:0] - Viterbi error count (low byte)
VIT_ERRCNT[15:8] - Viterbi error count (middle byte) R
This is effectively the QPSK Bit Error Rate. VIT_ERRCNT[23:0]: This is the count of bits corrected by the Viterbi decoder. This value is updated when the Viterbi error timer (VIT_ERRPER) expires (indicated by bit-2 in register FEC_INT) and is NOT reset by reading. QPSK_BER = VIT_ERRCNT[23:0] VIT_ERRPER[23:0] * 4
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Zarlink Semiconductor Inc.
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8.2.5 Reed-Solomon bit errors corrected registers 14 - 16 (R)
Design Manual
NAME RS_BERCNT_H RS_BERCNT_M RS_BERCNT_L
ADR 14 15 16
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
Def hex R 00 R 00
RS_BERCNT[23:16] - Reed-Solomon bit errors corrected (high byte) RS_BERCNT[7:0] - Reed-Solomon bit errors corrected (low byte)
RS_BERCNT[15:8] - Reed-Solomon bit errors corrected (middle byte) R 00
This is effectively the Viterbi Bit Error Rate. RS_BERCNT[23:0]: These three registers provide a measurement of the number of bit errors corrected by the Reed-Solomon decoder. Reading the high byte stops the count incrementing. Reading the low byte resets all three bytes and restarts the count incrementing again. Viterbi BER = RS_BERCNT[23:0] dt * Rs * 2 * CR
Where:
dt = delta time between two readings in sec (recommend 20s for 20 - 30 MS/s signals) Rs = symbol rate in Baud CR = Viterbi code rate In denominator: the factor 2 is for QPSK, change it to 1 for BPSK for Rs = 27.5MS/s, CR = 3/4 and dt = 20 sec
RS_BERCNT[23:0] RS_BERCNT[23:0] x 4 Viterbi BER = --------------------------------------------------------------- = -------------------------------------------------6 8 8.25 x 10 20 x ( 27.5 x 10 ) x 2 x 3
e.g.
8.2.6
Reed-Solomon uncorrected block errors registers 17 - 18 (R)
Def hex R R 00 00
NAME RS_UBC_H RS_UBC_L
ADR 17 18
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
RS_UBC[15:8] - Reed-Solomon uncorrected block errors (high byte) RS_UBC[7:0] - Reed-Solomon uncorrected block errors (low byte)
RS_UBC[15:0]: These two registers provide a measurement of the Reed-Solomon uncorrected block errors. Reading the high byte resets the byte and stops the count incrementing. Reading the low byte resets the byte and restarts the count incrementing again.
RS_UBC[15:0] x Blk_size Block error rate = ------------------------------------------------------------------dt x Rs x 2 x CR
where:
dt = delta time between two readings in sec Rs = symbol rate in Baud CR = Viterbi code rate Blk_size = 1632 bits for DVB and 1096 bits for DSS In denominator, the factor 2 is for QPSK, change it to 1 for BPSK
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9.0
9.1 9.1.1
Design Manual
Automatic Gain Control
Automatic gain control read/write registers AGC control register 39 (R/W)
Def hex R/W 26
NAME AGC_CTRL bit-7: bit-6: bit-5-4:
ADR 39
bit-7 Reserved
bit-6 Reserved
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0 AGC_SL
AGC_SD[1:0]
AGC_BW[2:0]
Reserved. Reserved. AGC_SD[1:0]
Must be set low. Must be set low. Sigma-Delta clock decimation ratio related to system clock.
AGC_SD[1:0] 00 01 10 11
Decimation 2 4 8 16
Table 6 - Sigma Delta Clock Decimation Ratio Programming AGC control output is a pulse density modulated output created by a sigma-delta modulator. To reduce power consumption this is not clocked at the full system clock rate. The frequency at which this is clocked is the system clock divided by the decimation factor in Table 6. bit-3-1: bit-0: AGC_BW[2:0] Front End AGC bandwidth (retain default value of 3).
AGC_SL Analogue AGC slope High = positive slope i.e. RF gain proportional to AGC voltage. Low = negative slope i.e. RF gain inversely proportional to AGC voltage (default).
9.1.2
AGC_REF Reference Value register 41 (R/W)
Def hex R/W 67
NAME AGC_REF AGC_REF[7:0]
ADR 41
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
AGC_REF[7:0] AGC reference level Front End AGC reference value.
The AGC loop control in MT312 is designed to bring the mean square value of the I signal (or the Q signal) at the ADC output (prior to any digital filtering) to the value set by the AGC_REF register.
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9.2 9.2.1 Automatic gain control read registers Measured signal level at MT312 input register 19 (R)
Def hex R 00
Design Manual
NAME SIG_LEVEL bits 7-0:
ADR 19
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
SIG_LEVEL[7:0] - Signal level at MT312 input
SIG_LEVEL[7:0]:
This register provides a measurement of the MT312 input signal level. When AGC is controlling the signal level, there is a direct relationship between SIG_LEVEL and AGC_REF: SIG_LEVEL * 8 = AGC_REF
Note:
the signal level is measured at the output of the ADC before any digital filtering takes place. Hence the reading includes all noise and other signal channels passed by the SAW or baseband filter.
9.2.2
Measured AGC feed back value registers 108 - 110 (R)
Def hex R R R 00 00 00
NAME AGC H AGC M AGC L AGC[13:0]:
ADR 108 109 110
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
AGC[13:6] - Front end AGC (high byte) AGC[5:0] - Front end AGC (low byte) ERR_DB[9:8]
ERR_DB[7:0] - Error difference (low byte)
These two registers provide a measurement of the AGC error feed back value by the MT312 to the front end. Reading the bytes does NOT reset the value.This measurement can be used to provide an indication of the signal level at the input to the tuner.
To avoid having too large a number, the following formula extracts a number less than 1024: Approximate input level = AGC[13-4]. ERR_DB[9:0]: The ERR_DB is the difference between the expected signal level defined by AGC_REF and received signal level. This is in a non-linear logarithmic scale (hence the notation DB). The way H/M/L registers work within the QPSK block is as follows. When the H register is read, the 24-bit value is copied into a shadow register. Reading the M and L registers is optional after this. It is NOT an option to read M and L (or just L of a 24 or 16-bit register) without reading H. The safest solution is to read H/M/L in that order.
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10.0
10.1
Design Manual
MPEG Packet Data Output
MPEG clock modes
There are four MOCLK modes of operation, controlled by register bits. MANUAL MOCLK (register 96 bit 7) 0 0 1 1 DIS_SR (register 97 bit 7) 0 1 0 1
MOCLK generation mode Use symbol rate for MOCLK generation. Disable use of symbol rate for MOCLK generation. Manually set MOCLK period from MOCLK_RATIO (reg. 33). Use external MICLK (pin 14) signal for MOCLK.
Table 7 - MPEG Clock Modes
10.1.1
MANUAL MOCLK = 0 and DIS_SR = 0.
In this mode MOCLK is generated from the symbol clock. MOCLK will be a continuously running clock once symbol lock has been achieved in the QPSK block.
10.1.2
MANUAL MOCLK = 0 and DIS_SR = 1.
In this mode MOCLK is not generated from the symbol clock but instead uses the data in the QPSK decimation ratio. This mode is not normally used but is available for engineering test purposes.
10.1.3
MANUAL MOCLK = 1 and DIS_SR = 0
This is the Programmable Clock Division Ratio mode of operation. MOCLK is generated by dividing the PLL clock frequency by the MOCLK_RATIO + 6 see register 33 on see "FEC_STATUS output enable register 33 (R/W)" on page 50. MOCLK frequency = PLL frequency (MCLK_RATIO + 6)
PLL Frequency 60MHz 60MHz 90MHz 91MHz
Moclk Ratio + 6 6 9 6 9
Moclk Frequency 10.0MHz 6.667MHz 15MHz 10.111MHz
Comment maximum minimum maximum minimum
Table 8 - MOCLK Input Minimum And Maximum Frequencies The range of values of 6 to 9 for (MOCLK_RATIO + 6) will guarantee operation for 2 - 45 MSym/s. However, for a restricted range of symbol rates, higher (MOCLK_RATIO + 6) values may be used with a lower MOCLK frequency. The equation in "Data output timing" on page 61 must be evaluated to ensure successful operation and avoid buffer overflow in the MT312.
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10.1.4 MANUAL MOCLK = 1 and DIS_SR = 1.
Design Manual
This is the External MPEG Clock mode of operation. The external MOCLK is input on the MICLK pin 14. The clock supplied must be a continuous clock, otherwise the data buffers in the MT312 would overflow and data would be lost. The maximum permitted MICLK frequency is: MICLK frequency maximum = PLL frequency 6.3
Where PLL frequency is 60MHz the MICLK frequency maximum = 9.524MHz. Where PLL frequency is 91MHz the MICLK frequency maximum = 14.444MHz. As in the Programmable Clock Division Ratio mode, the minimum MICLK frequency must be high enough to clock the complete MPEG packet out before the next one arrives. For this reason, the minimum MICLK frequency recommended is 6.7MHz at 60MHz and 10MHz at 90MHz. The MCLKINV control bit in the Output Data Control register (96) will change the phase of the MICLK used to clock the data out. With MCLKINV = 0, data are clocked out on the positive edge of MICLK. If MCLKINV = 1, data are clocked out on the negative edge of MICLK.
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10.2 Data Output Header Format - DVB
Design Manual
Figure 20 - DVB Transport Packet Header Bytes After decoding the 188 byte MPEG packet, it is output on the MDO pins in 188 consecutive clock cycles. Additionally, in DVB mode, when the EN_TEI bit in the OP_CTRL register (96) is set high (default), the TEI bit of any uncorrectable packet will automatically be set to 1, see page 62. If the EN_TEI bit is low, the TEI bit will not be changed (but note that if this bit is already 1, for example, due to a channel error which has not been corrected, it will remain high at output).
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10.3 MPEG/DSS Data Output Signals
Design Manual
MOCLK will be a continuously running clock once symbol lock has been achieved in the QPSK block and is derived from either the system clock or MICLK if external clock is selected. MOCLK is the MPEG data byte rate clock, the internal rate is calculated from the formulae in section 10.4. The maximum movement in the packet synchronisation byte position is limited to one output clock period. All output data and signals (MDO[7:0], MOSTRT, MOVAL, BKERR) change on the negative edge of MOCLK (MCLKINV = 1) to present stable data and signals on the positive edge of the clock. A complete packet is output on MDO[7:0] on 188 (DVB) or 130 (DSS) consecutive clocks and the MDO[7:0] pins will remain low during the inter packet gaps. MOSTRT goes high for the first byte clock of a packet. MOVAL goes high on the first byte of a packet and remains high until the 188th byte (DVB) or 130th byte (DSS) has been clocked out. BKERR has two modes of operation, selected by ERR_IND bit 7 of MON_CTRL register 103, see page 63.
10.3.1
ERR_IND = 0
BKERR remains high when error free MPEG packets are being output on the MDO[7:0] bus. BKERR goes low on the first byte of a packet where uncorrectable bytes are detected and will remain low until the 188th byte (DVB) or 130th byte (DSS) has been clocked out. BKERR also goes high when there is no de-scrambler lock, i.e. there are no MPEG packets being output.
When ERR_IND is Low:
Figure 21 - BKERR example when ERR_IND is low Figure 21 above shows lock being lost while ERR_IND is low. The event is divided into five significant periods: 1. Packets being received without errors. 2. Packets being received with errors. 3. Signal too poor for any packets to be received (lost lock). 4. Lock regained but packets still have errors. 5. Packets being received again with no errors.
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10.3.2 ERR_IND = 1
Design Manual
When ERR_IND is High:
BKERR remains high when error free MPEG packets are being output on the MDO[7:0] bus. BKERR goes low when there is no de-scrambler lock or on the first byte of a packet where uncorrectable bytes are detected. BKERR remains low until error free MPEG packets are being output on the MDO[7:0] bus.
Figure 22 - BKERR example when ERR_IND is high. Figure 22 above shows lock being lost while ERR_IND is high. The events are similar to the previous figure but BKERR remains low when signal lock is lost. Note: the signal on pin 75 can be inverted by setting the BKERIV bit 6 of OP_CTRL register 96, see page 62.
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10.4 Data output timing
Design Manual
The number of PLL clocks per Byte clock is: N= PLL Q*R*P 2*V * RS truncated to an integer
Where:
Q = 1 for QPSK, 2 for BPSK R = 204/193 for DVB, 147/135 for DSS P = 8 for parallel byte output, 1 for serial byte output V = Viterbi code rate, e.g. 3/4 for typical ASTRA signals PLL = Sampling frequency MHz RS = symbol rate in MS/s, e.g. 27.5MS/s for typical ASTRA signals
e.g. For DVB ASTRA
N N
= 1 * 204/193 * 8/2 * 4/3 *90E6/27.5E6 = 18 = PLL/N = 90E6/18 = 5E6Hz
The transport Stream clock rate
The time to transmit a packet
= 204 * 8/2 * 4/3 *1/RS = 1088/RS = 3.9564E-5 sec
Time to output 188 bytes
= 188/5E6 = 3.76E-5 sec
The gap between packets
= 3.9564E-5 - 3.76E-5 = 1.936E-6 sec
The gap as number of byte clocks
= 1.936E-6 * 5E6 = 9.82
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Design Manual
Figure 23 - MT312 Data Output Timing Diagram Parameter Data output delay (when MCLKINV = 1) Symbol tOD Min Typ 2 Max 4 Units ns
10.5 10.5.1
MPEG Packet Data Output Read/Write Registers Output data control register 96 (R/W)
Def hex R/W 33
NAME OP_CTRL bit-7: bit-6:
ADR 96
bit-7
bit-6
bit-5
bit-4
bit-3 bit-2 bit-1 bit-0 BA_LK[2:0]
MANUAL_MOCLK BKERIV MCLKINV EN_TEI BSO
MANUAL_MOCLK Manual MOCLK mode selection, see register 97 on page 50. BKERIV High = Inverted signal on BKERR output pin. Low = Normal signal on BKERR output pin.
bit-5:
MCLKINV
High = Normal signal on MOCLK output pin. Low = Inverted signal on MOCLK output pin.
For a description of how to use these features, see section 10.1 "MPEG clock modes" on page 56. With MCLKINV = 0, data are clocked out on the positive edge of MOCLK. If MCLKINV = 1, data are clocked out on the negative edge of MOCLK. bit-4: EN_TEI High = Enable automatic setting of transport error indicator (TEI) bit in MPEG packet header byte 2 when the block is flagged as uncorrectable by the Reed-Solomon decoder. See section 10.2 "Data Output Header Format - DVB" on page 58. (Not used in DSS). High = Bit serial output of the MPEG data on MDO0 pin. Low = Parallel output of the MPEG data on MDO[7:0] pins. bit-2 -0: BA_LK[2:0] + 2 = Number of bytes for byte aligner to lock. The default register value of 3 is equivalent to 5 good sync words.
bit-3:
BSO
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10.5.2 Monitor Control register 103 (R/W)
Def hex R/W 00
Design Manual
NAME MON_CTRL bit-7: High
ADR 103
bit-7 ERR_IND
bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 Reserved Error Indicator. MON_CTRL[3:0]
ERR_IND
BKERR remains high when error free MPEG packets are being output on the MDO[7:0] bus. BKERR goes low when there is no De-scrambler lock OR on the first byte of a packet where uncorrectable bytes are detected. BKERR will remain low until error free MPEG packets are being output on the MDO[7:0] bus. BKERR remains high when error free MPEG packets are being output on the MDO[7:0] bus. BKERR goes low on the first byte of a packet where uncorrectable bytes are detected and will remain low until the 188th byte (DVB) or 130th byte (DSS) has been clocked out. the BKERR signal on pin 75 can be inverted by setting the BKERIV bit 6, see page 62. Reserved, not used. MON_CTRL[3:0] selects which pair of registers will be read from MONITOR_H & L registers 123 and 124, (see section 7.2.4 "Monitor registers 123 - 124 (R)" on page 48). MON_CTRL[3:0] 0 1 2 3 4 5 6 7 8 15 - 9 MONITOR_H (123) CS_SYM_I DC_OFFSET_I Reserved MS/s OP_H Reserved DEC_RATIO[15:13] and the rest reserved M_FLD[7:0] M_TLD_H M_PLD_H Not used MONITOR_L (124) CS_SYM_Q DC_OFFSET_Q Reserved MS/s OP_L Reserved Reserved M_FLD7:0] M_TLD_L M_PLD_L Not used
Low
Note: bit-6-4: bit-3-0:
I and Q input samples when MON_CTRL[3:0] = 0. DC offset in the I and Q inputs when MON_CTRL[3:0] = 1. Symbol Rate when MON_CTRL[3:0] = 3, (see page 48). Decimation ratio when MON_CTRL[3:0] = 5, (see page 48). Timing synchroniser frequency lock detector value when MON_CTRL[3:0] = 6, (see page 48). Timing lock detector value when MON_CTRL[3:0] = 7, (see page 48). Phase lock detector value when MON_CTRL[3:0] = 8, (see page 48). The remaining settings of MON_CTRL[3:0] are either reserved for diagnostic purposes or not used.
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11.0
11.1
Design Manual
Secondary Registers for Test and De-Bugging
Read/Write Secondary Register Map
Def Page hex R/W 3B R/W FF R/W 00 R/W 0A R/W 1E R/W 14 66 66 66 66 66 66 66 66 67 67 67 67 67 67 67 67 68 68 68 68 68 68 69 69 69 69 69 69 70 70 70 70 70 70 70 70 70 71
Name AGC_INIT AGC_MAX AGC_MIN AGC_LK_TH TS_AGC_LK_TH AGC_PWR_SET QPSK_MISC SNR_THS_LOW SNR_THS_HIGH TS_SW_RATE TS_SW_LIM_L TS_SW_LIM_H CS_SW_RATE_1 CS_SW_RATE_2 CS_SW_RATE_3 CS SW RATE 4 CS_SW_LIM TS_LPK TS_LPK_M TS_LPK_L CS_KPROP_H CS_KPROP_L CS_KINT_H CS_KINT_L QPSK_SCALE TLD_OUTLK_TH TLD_INLK_TH FLD_TH PLD_OUTLK3 PLD_OUTLK2 PLD_OUTLK1 PLD_OUTLK0 PLD_INLK3 PLD_INLK2 PLD_INLK1 PLD_INLK0 PLD_ACC_TIME SWEEP_PAR
ADR 40 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59_ 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
AGC_INIT[7:0] Front end AGC initial value AGC_MAX[7:0] Front end AGC maximum value AGC_MIN[7:0] Front end AGC minimum value AGC_LK_TH[7:0] Front end AGC lock threshold value TS_AGC_LK_TH[7:0] Fine AGC lock threshold value AGC_PWR_SET[7:0] AGC power initial value DAGC_D A_OPEN MIX_D
CACC_D FOC_D TSLP_D CSLP_D ADC_FM R/W 00 R/W 5A R/W 46 R/W 1E R/W 40 R/W 84 R/W 20 R/W 48 R/W 70 R/W 90 R/W 7C R/W 57 TS_KINTE[11:8] TS_KINTE[7:0] R/W 85 R/W 9B CS_KP1[4:3] CS_KP0[4:0] CS_KI2[4:0] CS_KI0[4:0] CS_KI1[4:3] R/W 12 R/W 96 R/W 51 R/W 3B R/W 27 R/W 82 R/W 0A R/W 20 R/W AE R/W E6 R/W 40 R/W 7E R/W 01 R/W A0 R/W 68 R/W 1A R/W 48 R/W 49
SNR_THS_LOW[7:0] SNR estimator low threshold SNR_THS_HIGH[7:0] SNR estimator high threshold TS_SW_RATE[7:0] TS sweep rate TS_SW_LIM_L[7:0] TS sweep limit low TS_SW_LIM_H[7:0] TS sweep limit high CS_SW_RATE_1[7:0] CS sweep rate CS_SW_RATE_2[7:0] CS sweep rate CS_SW_RATE_3[7:0] CS sweep rate CS_SW_RATE_4[7:0] CS sweep rate CS SW LIM[7:0] CS sweep limit TS_KPROPE[11:4] TS_KPROPE[3:0]
NONSNR CS_KP1[2:0] Reserved CS_KI1[2:0]
CS_KP2[4:0]
QPSK_SCALE[7:0] QPSK output scale factor for IOUT and QOUT outputs TLD_OUTLK_TH[7:0] TLD threshold when not in lock TLD_INLK_TH[7:0] TLD threshold when in lock FLD_TH[7:0] Frequency lock threshold SW_R_N_MX[1:0] PLD_OUTLK3[3:0] PLD_OUTLK2[5:0] PLD_OUTLK1[7:0] Reserved PLD_INLK3[3:0]_ PLD_INLK2[5:0] PLD_INLK1[7:0] CS_PLD_MPLEN[3:0] SW_LIM_SC[1:0] TS_NR_SWEEP[2:0] LOSSLOCK_INT_SW[3:0] CS_NR_SWEEP[2:0] PLD_INLK3[9:4] PLD_INLK2[9:6] PLD INLK1 [9:8] PLD_OUTLK3[9:4] PLD_OUTLK2[9:6] PLD O LK1 [9:8]
Table 9 - Read/write Secondary Register Map
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Name STARTUP_TIME LOSSLOCK_TH FEC_LOCK_TM LOSSLOCK_TM VIT_ERRPER_H VIT_ERRPER_M VIT_ERRPER_L VIT_SETUP VIT_REF0 VIT_REF1 VIT_REF2 VIT_REF3 VIT_REF4_ VIT_REF5 VIT_REF6 VIT_MAXERR BA_SETUPT PROG_SYNC AFC_SEAR_TH ADR 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 98 99 BA_FSM[1:0] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
Design Manual
Def Page hex R/W 30 R/W 21 R/W 20 R/W 10 R/W FF R/W FF R/W FF EX_F_LK R/W 34 R/W 80 R/W 14 R/W 0A R/W 06 R/W 04 R/W 02 R/W 01 R/W FF R/W D4 R/W 47 R/W 23 R/W 20 R/W 04 R/W 00 71 71 71 72 72 72 72 72 73 73 73 73 73 73 73 73 74 74 74 74 74 75 75 75 75 75
STARTUP_INTERVAL[7:0] LOSSLOCK_TH_SPUR[3:0] LOSSLOCK_TH_SW[3:0]
FEC_LOCK_TIME[7:0] LOSSLOCK_TIME[7:0] VIT_ERRPER[23:16] Viterbi error period (high byte) VIT_ERRPER[15:8] Viterbi error period (middle byte) VIT_ERRPER[7:0] Viterbi error period (low byte) FR_AL_TM_O[1:0] SRCH_CYC[1:0] SEARCH_START[2:0]
VIT_REF0[7:0] Viterbi reference byte 0 VIT_REF1[7:0] Viterbi reference byte 1 VIT_REF2[7:0] Viterbi reference byte 2 VIT_REF3[7:0] Viterbi reference byte 3 VIT_REF4[7:0] Viterbi reference byte 4 VIT_REF5[7:0] Viterbi reference byte 5 VIT_REF6[7:0] Viterbi reference byte 6 VIT_MAXERR[7:0] Viterbi max. error bit count BA_MV_[1:0] BA_UNLK[3:0]
PROG_SYNC_BYTE[7:0] Enabled by FEC_SETUP [2] AFC_SEAR_TH[7:0] ACC_DIF_TH[7:0] CS_LLK TS_LLK ACC_CK NUM_PLD_INT[4:0] FORCED_ST[2:0] PR_TS PR_FE
CSACC_DIF_TH 100 QPSK_LK_CT QPSK_ST_CT
QPSK_RESET
101 102 104 105 106 125
HLD_ST AFC_RS M_SRS NXT_FR FCE_ST Reserved REL_QP PR_QP PR_CS
PR_AGC R/W 00 R/W 00 R/W 00 R/W 00
QPSK_TST_CT QPSK_TST_ST TEST_MODE
QPSK_TEST_CTRL[7:0] QPSK_TEST_TS[7:0] Test mode
Table 9 - Read/write Secondary Register Map (continued)
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11.2 11.2.1 Secondary Registers for Test and De-Bugging Read/Write Registers AGC Initial Value register 40 (R/W)
Default value Front End AGC initial value. 59 dec. 3B hex.
Design Manual
AGC INIT (40) AGC INIT[7:0]
11.2.2
AGC Maximum Value register 42 (R/W)
Default value 255 dec. FF hex.
AGC MAX (42) AGC MAX[7:0]
Front End AGC maximum value.
11.2.3
AGC Minimum Value register 43 (R/W)
Default value Front End AGC minimum value. 0 dec. 00 hex.
AGC MIN (43) AGC MIN[7:0]
11.2.4
AGC Lock Threshold Value register 44 (R/W)
Default value 10 dec. 0A hex.
AGC LK TH (44) AGC LK TH[7:0]
Front End AGC lock threshold value.
11.2.5
AGC Lock Threshold Value register 45 (R/W)
Default value 30 dec. 1E hex.
TS AGC LK TH (45) TS AGC LK TH[7:0]
Timing synchroniser fine AGC lock threshold value.
11.2.6
AGC Power Setting Initial Value register 46 (R/W)
Default value 20 dec. 14 hex.
AGC PWR SET (46) AGC PWR AGC SET[7:0]
power setting initial value.
11.2.7
QPSK Miscellaneous register 47 (R/W)
Default value Reserved, must be set low, 0 dec. 00 hex.
QPSK MISC (47) QPSK MISC[bit-7-0]
11.2.8
SNR_LOW threshold value register 48 (R/W)
Default value 90 dec. 5A hex.
SNR_THS_LOW (48) SNR THS LOW[7:0]
SNR low threshold value.
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11.2.9 SNR_HIGH threshold value register 49 (R/W)
Default value 70 dec. 46 hex.
Design Manual
SNR_THS_HIGH (49) SNR_THS_HIGH[7:0]
SNR high threshold value.
Change to 50 dec. 32 hex. after a full reset.
11.2.10
Timing Synchronisation Sweep Rate register 50 (R/W)
Default value 30 dec. 1E hex.
TS_SW_RATE (50) TS SW RATE[7:0]
Timing Synchronisation sweep rate. For DSS set the value to 20 dec. 14 hex. after a full reset.
11.2.11
Timing Synchronisation Sweep Limit Low register 51 (R/W)
Default value 64 dec. 40 hex.
TS SW LIM L (51) TS SW LIM L[7:0]
Timing Synchronisation sweep limit low.
11.2.12
Timing Synchronisation Sweep Limit High register 52 (R/W)
Default value 132 dec. 84 hex.
TS SW LIM H (52) TS SW LIM H[7:0]
Timing Synchronisation sweep limit high.
11.2.13
Carrier Synchronisation Sweep Rate 1 register 53 (R/W)
Default value 32 dec. 20 hex.
CS SW RATE 1 (53) CS SW RATE 1[7:0]
Carrier Synchronisation sweep rate 1.
11.2.14
Carrier Synchronisation Sweep Rate 2 register 54 (R/W)
Default value 72 dec. 48 hex.
CS SW RATE 2 (54) CS SW RATE 2[7:0]
Carrier Synchronisation sweep rate 2
11.2.15
Carrier Synchronisation Sweep Rate 3 register 55 (R/W)
Default value 112 dec. 70 hex.
CS SW RATE 3 (55) CS SW RATE 3[7:0]
Carrier Synchronisation sweep rate 3.
11.2.16
Carrier Synchronisation Sweep Rate 4 register 56 (R/W)
Default value 144 dec. 90 hex.
CS SW RATE 4 (56) CS SW RATE 4[7:0]
Carrier Synchronisation sweep rate 4.
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11.2.17
CS SW LIM (57) CS SW LIM[7:0]
Design Manual
Carrier Synchronisation Sweep Limit register 57 (R/W)
Default value 124 dec. Carrier Synchronisation sweep limit. 7C hex.
11.2.18
Timing Synchronisation Coefficients registers 58 - 60 (R/W)
Def hex R/W R/W R/W 57 85 9B
NAME TS LPK H TS LPK M TS LPK L bit-23-12: bit-11-0: TS
ADR 58 59 60
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
TS KPROPE[11:4] TS KPROPE93:0] TS KINTE[7:0] TS KINTE[11:8]
TS KPROPE[11:0] KINTE [11:0]
Timing Synchronisation Proportional path coefficients. Timing Synchronisation Integration path coefficients.
11.2.19
Carrier Synchronisation Proportional Part Coefficients registers 61 - 62 (R/W)
Def hex R/W R/W 12 3B
NAME CS KPROP_H CS KROP_L bit-15: bit-14-10: bit-9-5: bit-4-0:
ADR 61 62 NONSNR CS KP2[4:0] CS KP14:0] CS KP04:0]
bit-7 NON SNR
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
CS KP2[4:0]
CS KP1[4:3] CS KP0[p4:0]
CS KP1 [2:-0]
High = Non SNR sweep. Carrier proportional tracking coefficients. Carrier proportional transition coefficients. Carrier proportional acquire coefficients.
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11.2.20 Carrier Synchronisation Integral Coefficients registers 63 - 64 (R/W)
bit6 bit5 bit4 bit3 bit2
Design Manual
NAME CS KINT H CS KINT L bit-15: bit-14-10: bit-9-5: bit-4-0:
ADR 63 64 Reserved CS KI2 [4:0] CS KI1 [4:0] CS KI0[4:0]
bit-7 Reserved
bit-1
bit-0 R/W R/W
Def hex 51 3B
CS KI2[4:0]
CS KI1[4:3] CS KI0[4:0]
CS KI1[2:0]
Carrier integer tracking coefficients. Carrier integer transition coefficients. Carrier integer acquire coefficients.
11.2.21
QPSK Output Scale Factor register 65 (R/W)
Default value 39 dec. 27 hex.
QPSK SCALE (65) QPSK SCALE [7:0]
QPSK output scale factor for IOUT and QOUT outputs.
11.2.22
Timing Lock Detect Threshold out of lock register 66 (R/W)
Default value 130 dec. 82 hex.
TLD OUTLK TH (66)
TLD OUTLK TH [7:0]Timing Lock Detect threshold when not in lock.
11.2.23
Timing Lock Detect Threshold in lock register 67 (R/W)
Default value 10 dec. 0A hex.
TLD INLK TH (67) TLD INLK TH[7:0]
Timing Lock Detect threshold when in lock.
11.2.24
Frequency Lock Detect Threshold register 68
Default value 32 dec. 2 0 hex.
FLD TH (68) FLD TH[7:0]
Frequency lock detect threshold.
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11.2.25 Phase Lock Detect Threshold out of lock registers 69 - 72 (R/W)
bit7 bit6 bit5 bit4 bit3 bit2
Design Manual
NAME PLD OUTLK3 PLD OUTLK2 PLD OUTLK1 PLD OUTLK0 bit-31-30: bit-29-20: bit-19-10: bit-9-0:
ADR 69 70 71 72
bit-1
bit-0 R/W R/W R/W R/W
Def hex AE E6 40 7E
SW R N MX[1:0] PLD OUTLK3[3:0] PLD OUTLK2[5:0]
PLD OUTLK3[9:4] PLD OUTLK2[9:6] PLD O LK1[9:8]
PLD OUTLK1[7:0] CS Sweep rate number max.
SW R N MX[1:0] PLD OUTLK TH3[9:0] PLD OUTLK TH2[9:0] PLD OUTLK TH1[9:0]
11.2.26
Phase Lock Detect Threshold in lock registers 73 - 76 (R/W)
bit6 bit5 bit4 bit3 bit2 Def hex R/W PLD INLK2[9:6] R/W PLD INLK1 [9:8] R/W 01 A0 68 1A
NAME PLD INLK3 PLD INLK2 PLD INLK1 PLD INLK0 bit-31-30: bit-29-20: bit-19-10: bit-9-0:
ADR 73 74 75 76 Reserved
bit-7
bit-1
bit-0
Reserved PLD INLK3[3:0] PLD INLK2[5:0] PLD INLK1[7:0]
PLD INLK TH3[9:0] PLD INLK TH2[9:0] PLD INLK TH1[9:0]
11.2.27
Phase Lock Detect Accumulator Time register 77 (R/W)
bit6 bit5 bit4 bit3 bit2 Def hex R/W 48
NAME PLD ACC TIME bit-7-4: bit-3-0:
ADR 77
bit-7
bit-1
bit-0
CS PLD MPLEN[3:0]
LOSSLOCK INT SW[3:0]
CS PLDMPLEN[3:0] LOSSLOCK INT SW[3:0]
Maximum value allowed is 8.
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11.2.28 Sweep PAR register 78 (R/W)
Design Manual
NAME SWEEP PAR bit-7-6: bit-5-3: bit-2-0:
ADR 78
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0 R/W
Def hex 49
SW LIM SC [1:0]
TS NR SWEEP[2:0]
CS NR SWEE{[2:0]
SW LIM SC[1:0] TS NR SWEEP[2:0] CS NR SWEEP[2:0]
Frequency sweep limit scale.
11.2.29
Start up Time register 79 (R/W)
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 R/W Def hex 30
NAME STARTUP TIME STARTUP INTERVAL[7:0]
ADR 79
STARTUP INTERVAL[7:0]
11.2.30
Loss Lock Threshold register 80 (R/W)
Def hex R/W 21
NAME LOSSLOCK TH bit-7-4: bit-3-0:
ADR 80
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
LOSSLOCK TH SPUR[3:0]
LOSSLOCK TH SW[3:0]
LOSSLOCK TH SPUR[3:0] LOSSLOCK TH SW[3:0]
11.2.31
FEC Lock Time register 81 (R/W)
Default value 32 dec. 20 hex.
FEC LOCK TM (81). FEC LOCK TM[7:0]
The number of symbol periods which the QPSK allows for the FEC to lock after achieving carrier and timing synchronisation is given by: FEC LOCK TM * Search factor * 65536 The parameter Search Factor is 1 if there is no code rate search and is 8 if there is a code rate search, i.e. the QPSK allows more time for the FEC to lock in the presence of a code rate search. If the FEC does not lock within the allotted number of symbol periods, then the QPSK resets the timing and carrier loops and resumes the search for a QPSK signal.
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11.2.32 Loss Lock Time register 82 (R/W)
Default value 16 dec. 10 hex.
Design Manual
LOSSLOCK TM (82) LOSSLOCK TM[7:0]
After the FEC locks it can unlock due to a signal fade or a cycle slip. Then the QPSK allows the following number of symbol periods for the FEC to regain lock: LOSSLOCK TM * 262144 If the FEC does not regain lock during this number of symbol periods, then QPSK will re-acquire lock.
11.2.33
Viterbi Error Period registers 83 - 85 (R/W)
Default value 16,777,215 dec.FF FF FF hex.
VIT ERRPER (83, 84 & 85) VIT ERRPER [23:0]
Viterbi error period. This is the period over which the Viterbi error count is measured. See Section 8.2.4 "Viterbi error count at Viterbi input registers 11 - 13 (R)" on page 52.
11.2.34
Viterbi Set up register 86 (R/W)
Def hex R/W 34
NAME VIT_SETUP
ADR 86
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0 EX F LK
FR AL TM O[1:0]
SRCH CYC [1:0]
SEARCH START [2:0]
bit-7-6: bit-5-4: bit-3-1:
FR AL TM O [1:0] SRCH CYC[2:0] SEARCH START[2:0]
Frame (or byte) align time out. Viterbi BER based search cycles. Code rate search start, only one code rate may be selected.
bit-6-4 0 1 2 3 4 5
Code rate search start at: 1/2 2/3 3/4 5/6 6/7 7/8
Table 10 - Viterbi Code Rate Search Start bit-0: EX F LK Exit false lock.
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11.2.35 Viterbi Reference Byte 0 register 87 (R/W)
Default value Viterbi reference byte 0. 128 dec. 80 hex.
Design Manual
VIT REF0 (87) VIT REF0[7:0]
11.2.36
Viterbi Reference Byte 1 register 88 (R/W)
Default value Viterbi reference byte 1. 20 dec. 14 hex.
VIT REF1 (88) VIT REF1[7:0]
11.2.37
Viterbi Reference Byte 2 register 89 (R/W)
Default value Viterbi reference byte 2. 10 dec. 0A hex.
VIT REF2 (89) VIT REF2[7:0]
11.2.38
Viterbi Reference Byte 3 register 90 (R/W)
Default value Viterbi reference byte 3. 6 dec. 06 hex.
VIT REF3 (90) VIT REF3[7:0]
11.2.39
Viterbi Reference Byte 4 register 91 (R/W)
Default value Viterbi reference byte 4. 4 dec. 04 hex.
VIT REF4 (91) VIT REF4[7:0]
11.2.40
Viterbi Reference Byte 5 register 92 (R/W)
Default value Viterbi reference byte 5. 2 dec. 02 hex.
VIT REF5 (92) VIT REF5[7:0]
11.2.41
Viterbi Reference Byte 6 register 93 (R/W)
Default value Viterbi reference byte 6. 1 dec. 01 hex.
VIT REF6 (93) VIT REF6[7:0]
11.2.42
Viterbi Maximum Error register 94 (R/W)
Default value 148 dec. 94 hex.
VIT_MAXERR (94)
VIT_MAXERR[7:0] Viterbi maximum error. This register controls the frequency of the BER indication audio signal, output on the status pin when the FEC_STAT_EN register bit-0 is set high, see pages 13 and 50.
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11.2.43 Byte Align Set up register 95 (R/W)
Design Manual
NAME BA SETUP bit-7-6: bit-5-4: bit-3-0:
ADR 95
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0 R/W
Def hex D4
BA FSM[1:0]
BA MV[1:0]
BA UNLK[3:0]
BA FSM[1:0] MA MV[2:0] + 5 = BA UNLK[3:0] +3 =
Byte Align FSM mode. Byte Align majority voting. Number of bad sync words to unlock the Byte Align. The default register value of 4 is equivalent to 7 bad sync words.
11.2.44
Program Synchronising Byte register 98 (R/W)
Default value 71 dec. 47 hex.
PROG SYNC (98) PROG SYNC[7:0]
If FEC_SETUP[2] is high, use the PROG SYNC value to synchronise MPEG data packets.
11.2.45
AFC Frequency Search Threshold register 99 (R/W)
Default value 35 dec. 23 hex.
AFC SEAR TH (99) AFC SEAR TH[7:0]
11.2.46
Accumulator Differential Threshold register 100 (R/W)
Default value 32 dec. 20 hex.
CSACC DIFF TH (100) CSACC DIFF TH[7:0]
11.2.47
QPSK Lock Control register 101 (R/W)
bit4 bit3 bit2 bit1 bit0 R/W Def hex 04
NAME QPSK LK CT bit-7: bit-6: bit-5: bit-4-0:
ADR 101 CS L LK TS L LK ACC CK
bit-7 CS L LK
bit-6 TS L LK
bit-5 ACC CK
NUM_PLD INT[4:0]
High = Use CS long lock. High = Use TS long lock. High = Disable Accumulator check option. Maximum value allowed is 29.
NUM_PLD INT[4:0]
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11.2.48 QPSK State Control register 102 (R/W)
bit2 bit1
Design Manual
NAME QPSK ST CT bit-7: bit-6: bit-5: bit-4: bit-3: bit-2-0:
ADR 102
bit-7 HLD ST
bit-6 AFC RS
bit-5 M S RS
bit-4 NXT FR
bit-3 FCE ST
bit0 R/W
Def hex 00
FORCED ST[2:0]
HLD ST AFC RS M S RS NXT FR FCE ST FORCED ST[2:0]
High = Hold state. High = AFC reset. High = Mixer scan reset. High = Get next frequency. High = Force state. Forced state.
11.2.49
QPSK Reset register 104 (R/W)
bit7 bit6 Def hex R/W 00
NAME QPSK RESET
ADR 104
bit-5 REL QP
bit-4 PR_Q P
bit-3 PR CS
bit-2 PR TS
bit-1 PR FE
bit-0 PR AGC
Reserved
bit-7-6: bit-5: bit-4: bit-3: bit-2: bit-1: bit-0:
Reserved Must be set low. REL QP PR_QP PR CS PR TS PR FE PR AGC High = Release QPSK FSM. High = Partial reset FSM (applies to QPSK control). High = Partial reset carrier synchroniser High = Partial reset timing synchroniser (includes fine AGC). High = Partial reset front-end logic. High = Partial reset analogue AGC.
11.2.50
QPSK Test Control register 105 (R/W)
Default value 0 dec. 00 hex.
QPSK_TST CT (105) QPSK TEST CTRL[7:0]
For factory test purposes only.
11.2.51
QPSK Test State register 106 (R/W)
Default value 0 dec. 00 hex.
QPSK TEST ST (106) QPSK TEST ST[7:0]
For factory test purposes only.
11.2.52
Test Mode register 125 (R/W)
Default value 0 dec. 00 hex.
TEST MODE (125) TEST MODE[7:0]:
This register is for testing purposes only.
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11.3 Read only Secondary Register Map
Design Manual
Writing to these registers will have no effect.
NAME TEST R
ADR 107
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0 R
Def hex 00
TEST R[7:0] Test Read, for test purposes only.
11.4 11.4.1
Secondary Registers for Test and De-Bugging Read Register Test Read register 107 (R)
Default value 0 dec. 00 hex.
TEST R (107) TEST R[7:0]
For test purposes only.
12.0
12.1
Microprocessor Control
Primary 2-wire Bus Address
The 2-wire bus Address is determined by applying VDD or VSS to the ADDR[7:1] pins. See Primary 2-wire Bus Interface.
12.2
RADD: 2-wire Register Address (W)
RADD is the 2-wire register address. It is the first byte written after the MT312 2-wire chip address when in write mode. To write to the chip, the microprocessor should send a START condition and the chip address with the write bit set, followed by the register address where subsequent data bytes are to be written. Finally, when the 'message' has been sent, a STOP condition is sent to free the bus. To read from the chip from register address zero, the microprocessor should send a START condition and the chip address with the read bit set, followed by the requisite number of CLK1 clocks to read the bytes out. Finally a STOP condition is sent to free the bus. RADD is not sent in this case. To read from the chip from an address other than zero, the microprocessor should send the chip address with the write bit set, followed by the register address where subsequent data bytes are to be read. Then the microprocessor should send a START condition and the chip address with the read bit set, followed by the requisite number of CLK1 clocks to read the bytes out. Finally a STOP condition is sent to free the bus. A STOP condition resets the RADD value to 00. For examples of use, see "Examples of 2-wire Bus Messages" on page 78. RADD (virtual register, address none)
NAME RADD bit-7:
ADR N/A
bit-7 IAI IAI
bit-6 AD6
bit-5 AD5
bit-4 AD4
bit-3 AD3
bit-2 AD2
bit-1 AD1
bit-0 AD0 W
Def hex -
High = Inhibit auto increment. Low = Increment addresses.
bit-6-0:
AD[6:0]
2-wire register address, numbers in the range 0 to 127 are allowed.
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Design Manual
When the register address is incremented to 127 it stops and the bus will continue to write to or read from register 127 until a STOP condition is sent.
12.3
Primary 2-wire Bus Interface
The primary 2-wire bus serial interface uses pins: DATA1 (pin 54) Serial data, the most significant bit is sent first. CLK1 (pin 53) Serial clock. The 2-wire bus Address is determined by applying VDD or VSS to the ADDR[7:1] pins. For compatibility with earlier devices, the 2-wire bus address should be 0001 110 R/W and the pins connected as follows: ADDR[7] VSS ADDR[6] VSS ADDR[5] VSS ADDR[4] VDD ADDR[3] VDD ADDR[2] VDD ADDR[1] VSS
When the MT312 is powered up, the RESET pin 49 should be maintained low for typically 250ms (minimum 100ms) after VDD has reached normal operation levels. This is to ensure that the crystal oscillator and internal PLL have become fully established and that the internal reset signal is fully clocked into all parts of the circuit. As the reset pin is pulled high, the logic levels on ADDR[7:1] are latched to become the 2-wire bus address AD[6:0]. IIN[5:1] are only used for test purposes and should be wired to VSS. The circuit works as a slave transmitter with the eighth bit set high or as a slave receiver with the eighth bit set low. In receive mode, the first data byte is written to the RADD virtual register, which forms the register sub-address. Bit 7 of the RADD register, IAI is an Inhibit Auto Increment function. When the IAI bit is set high, the automatic incrementing of register addresses is inhibited. IAI set low is the normal situation so that data bytes sent on the 2-wire bus after the RADD register data are loaded into successive registers. This automatic incrementing feature avoids the need to individually address each register. Following a valid chip address, the 2-wire bus STOP command resets the RADD register to 00. If the chip address is not recognised, the MT312 will ignore all activity until a valid chip address is received. The 2-wire bus START command does NOT reset the RADD register to 00. This allows a combined 2-wire bus message to point to a particular read register with a write command, followed immediately with a read data command. If required, this could next be followed with a write command to continue from the latest address. Finally a STOP command should be sent to free the bus. When the 2-wire bus is addressed (after a recognised STOP command) with the read bit set, the first byte read out will be the content of register 00.
12.4
Secondary 2-wire bus for tuner control
The MT312 has a General Purpose Port that can be configured to provide a secondary 2-wire bus with full bi-directional operation. When pass-through is enabled, a transparent connection is made to the tuner. This innovative design simplifies the software required to program the tuner to only five data bytes. Pass-through mode is selected by setting register (20) GPP_CTRL[bit-6] = 1. The allocation of the pins is: GPP[0] pin 44 = CLK2, GPP[1] pin 45 = DATA2.
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12.5
KEY:
Design Manual
Examples of 2-wire Bus Messages
S P A RADD Start condition Stop condition Acknowledge Register Address W R NA ITALICS Write (= 0) Read (= 1) NOT Acknowledge MT312 output
Write operation - as a slave receiver: S DEVICE ADDRESS W A RADD (n) A DATA (reg n) A DATA (reg n+1) A P
Read operation - MT312 as a slave transmitter: S DEVICE ADDRESS R A DATA (reg 0) A DATA (reg 1) A DATA (reg 2) NA P
Write/read operation with repeated start - MT312 as a slave transmitter: S DEVICE ADDRESS W A RADD (n) A S DEVICE ADDRESS R A DATA (reg n) A DATA reg n+1) NA P
Write/read/write operation with repeated start and auto increment off with IAI set high - MT312 as a slave transmitter. This example uses the GPP_CTRL register where the register address is 20 + 128 (IAI). Data are first read from the GPP_CTRL register, then following a restart, data are written to the GPP_CTRL register. S DEVICE W A RADD A S DEVICE R A DATA NA S DEVICE W A DATA A P ADDRESS (148) ADDRESS (reg 20) ADDRESS (reg 20)
To program the Tuner, use the following sequence of three messages: Open secondary 2-wire port: S MT312 ADDRESS W A GPP_CTRL (20) A DATA (64) A P
Program Tuner: S TUNER ADDRESS W A DATA (BYTE 2) A DATA (BYTE 3) A DATA (BYTE 4) A DATA (BYTE 5) A P
Close secondary 2-wire port: S MT312 ADDRESS W A GPP_CTRL (20) A DATA (0) A P
Always close the secondary 2-wire port after programming the Tuner, to avoid 2-wire bus clock interference in the Tuner.
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12.6 Primary 2-wire Bus Timing
Design Manual
Figure 24 - Primary 2-wire Bus Timing Where: S = Start Sr = Restart, i.e. Start without stopping first. P = Stop.
Value Parameter: Primary 2-wire bus only CLK1 clock frequency Bus free time between a STOP and START condition. Hold time (repeated) START condition. LOW period of CLK1 clock. HIGH period of CLK1 clock. Set-up time for a repeated START condition. Data hold time (when input). Data set-up time Rise time of both CLK1 and DATA1 signals. Rise time of both CLK1 and DATA1 signals, (100pF to ground) Set-up time for a STOP condition. Symbol Min fCLK tBUFF tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tR tF tSU;STO Table 11 - Primary 2-wire bus timing
Note 1: The rise time depends on the external bus pull-up resistor.
Unit Max 450 kHz ns ns ns ns ns ns ns note 1 20 200 ns ns ns 0 200 200 450 600 200 100 100
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13.0
13.1
Design Manual
Electrical Characteristics
Recommended Operating Conditions
Recommended Operating Conditions Parameter Core power supply voltage Core power supply current Power supply voltage Power supply current Input clock frequency 1 CLK1 clock frequency Ambient operating temperature Symbol CVDD CIDD VDD IDD XTI FCLK1 0 9.99 3.0 Min 1.62 Typ 1.8 130 3.3 170 Max 1.98 150 3.6 220 16.00 450 70 Units V mA V mA MHz kHz C
Note 1:
When not using a crystal, XTI may be driven from an external source over the frequency range shown.
13.2
Absolute Maximum Ratings
Maximum Operating Conditions Parameter Power supply Voltage on input pins (5 v rated) Voltage on input pins (3.3v rated) Voltage on input pins (1.8v rated) Voltage on output pins (5v rated) Voltage on output pins (3.3v rated) Voltage on output pins (1.8v rated) Storage temperature Operating ambient temperature Junction temperature
Note 1:
Symbol VDD VI VI VI VO VO VO TSTG TOP TJ
Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -55 0
Max +3.6 5.5 VDD+ 0.3 CVDD + 0.3 5.5 VDD + 0.3 CVDD + 0.3 150 70 125
Unit V V V V V V V C C C
Stresses exceeding these listed under 'Absolute Ratings' may induce failure. Exposure to absolute maximum ratings for extended periods may reduce reliability. Functionality at or above these conditions is not implied.
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13.3 Crystal Specification
9.99 to 16.00MHz. 25ppm. 50ppm. 30pF. <35
Design Manual
Parallel resonant fundamental frequency (preferred) Tolerance over operating temperature range Tolerance overall Nominal load capacitance Equivalent series resistance
Figure 25 - Crystal Oscillator Circuit Note: The crystal frequency should be chosen to ensure that the system clock would marginally exceed the maximum symbol rate required.
13.4
Electrical Characteristics
DC Electrical Characteristics Parameter Core operating voltage Peripheral operating voltage Average core power supply current Average peripheral power supply current Average supply current Stand-by Mode Output levels VOH Tri-state push pull 1 mA drive current. IIN, QIN, TESTCLK, MDO, MOVAL, MOSTRT, MOCLK, BKERR, DISECQ, STATUS 1 mA drive current, Pins as VOH. VOH 0.80 VDD Conditions/Pin Symbol CVDD VDD CIDD IDD Min. 1.62 3.0 Typ. 1.8 3.3 130 170 1 Max. 1.98 3.6 150 220 2 Unit V V mA mA mA
0.92 VDD
V
Output levels VOL Tri-state push pull
0.2
0.4
V
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DC Electrical Characteristics (continued) Parameter Output level open drain Conditions/Pin 4 mA drive current. 6 mA drive current. AGC, DATA1, IRQ, GPP<2:0> 3.3V input CMOS 5.0V input VIH VIH VIL VIN = 0 and VDD 0.7 VDD 0.7 VDD Symbol Min. Typ.
Design Manual
Max. 0.4 0.6
Unit V V
Input levels VIH CMOS Input levels VIH Input levels VIL CMOS Input leakage Current
V V VIL 0.3VDD 10 V A
13.5
MT312 Pinout Description
Pin Description Table Pin 4,5,6,7, 8,11,12 14 Name ADDR[7:1] MICLK Description Primary 2-wire bus address defining pins MPEG clock input used to generate MOCLK. Enabled when both register 96 bit 7 and register 97 bit 7 are set high. In this mode, MICLK must be continuous. External ADC mode clock. Crystal clock input or external reference clock input. Crystal output. An internal feedback resistor to XTI is included Phase Locked Loop test output ADC Voltage top reference level I channel de-coupling input I channel input No connection ADC Voltage middle reference level Q channel input Q channel de-coupling input ADC Voltage bottom reference level Bias level For factory test only. This pin must be connected to VSS in normal operation For factory test only. This pin must be connected to VSS in normal operation I I CMOS CMOS 3.3 3.3 I I I/O I/O I Note CMOS CMOS V 3.3 51 mA 1
16 18 19 23 26 27 28 29 32 33 34 35 38 39 40
TESTCLK
O I O 23 26 I I I
PECL CMOS CMOS
Tri-state 3.3 3.3
3.3
XTI
XTO PLL1 VRT IREF ISINGP NC VRM QSINGP QREF VRB RREF TEST1 TEST2
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Pin Description Table (continued) Pin 43 46,45,44 Name AGC GPP[2:0] (DISEQC2) AGC sigma-delta output General Purpose Port for tuner control, register defined. GPP0 = secondary CLK2, GPP1 = secondary DATA2, GPP2 = DiSEqCTM v2.2 input signal. DiSEqCTM Horizontal/Vertical control DiSEqCTM 22kHz output Active low reset input Audio BER or Status output, register defined 2-wire serial bus clock 2-wire serial bus data Active low interrupt output. A low output on this pin indicates an event has occurred and the microprocessor should read the interrupt registers. Reading all interrupt registers resets this pin. MPEG clock output at the data byte rate. O O I O I I/O O Description I/O O I/O Note Open drain Open drain
Design Manual
V 51 51
mA 6 6
47 48 49 52 53 54 57
DISEQC1 DISEQC0 RESET STATUS CLK1 DATA1 IRQ
CMOS CMOS CMOS CMOS CMOS Open drain Open drain
3.3 3.3 5 3.3
1 1 1 1
51 51
6 6
58
MOCLK
O
CMOS Tri-sta te CMOS Tri-sta te CMOS CMOS Tri-sta te CMOS Tristate CMOS Tristate
3.3
1
69,68,66 ,65, 64,63,61 ,59 71 72
MDO[7:0]
MPEG transport packet data output bus.
O
3.3
1
MDOEN MOVAL
Logic 1 = MPEG data and clock outputs disable - Tri-state. Logic 0 = MPEG data and clock outputs enable MPEG data output valid. This pin is high during the MOCLK clock cycles when valid data bytes are being output.
I O
51 3.3 1
75
BKERR
Active low uncorrectable block indicator OR no signal indicator selected by ERR_IND bit 7 of MON_CTRL register.
O
3.3
1
76
MOSTRT
MPEG output start signal, high on the first byte of a packet.
O
3.3
1
2,9,17,4 2,50, 55,62,67 13,73 37 30 25 21
CVDD
Core Digital CVDD. All pins must be connected.
1.8
VDD ADCAVDD ADCDVDD ADCFVDD PLLVDD
Peripheral VDD. All pins must be connected. ADC core analogue VDD. All pins must be connected. ADC core digital VDD. All pins must be connected. ADC core front end VDD. All pins must be connected. PLL VDD. All pins must be connected.
3.3 1.8 3.3 3.3 1.8
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Pin Description Table (continued) Pin 1,10,20, 41, 51, 60,70 15,56,74 36 31 53 24 22 77,78,79 , 80,3
Note 1:
Design Manual
Name CVSS
Description Digital VSS. All pins must be connected.
I/O
Note
V
mA
VSS ADCAGND ADCDGND CLK1 ADCFGND PLLGND IIN[5:1]
Peripheral VSS. All pins must be connected. ADC core analogue VSS. Must be connected to analogue GND. ADC core digital VSS. Must be connected to analogue GND. 2-wire serial bus clock ADC core front end VSS. Must be connected to analogue GND. PLL VSS. Must be connected to analogue GND. Test bus, all inputs must be connected to VSS. I/O CMOS I CMOS
0 0 0 51 0 0 3.3 1
5V tolerant pins with thresholds related to 3.3V.
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13.6 Alphabetical Listing of Pin-Out
Design Manual
Alphabetical Listing of Pin-Out FUNCTION ADCAGND ADCAVDD ADCDVDD ADCDGND ADCFGND ADCFVDD ADDR[1] ADDR[2] ADDR[3] ADDR[4] ADDR[5] ADDR[6] ADDR[7] AGC BKERR CLK1 CLK2/GPP0 NC CVDD CVDD PIN 36 37 30 31 24 25 12 11 8 7 6 5 4 43 75 53 44 29 2 9 FUNCTION CVDD CVDD CVDD CVDD CVDD CVSS CVSS CVSS CVSS CVSS CVSS CVSS DATA1 DATA2 /GPP1 DISEQC0 22kHz DISEQC1 DISEQC2 /GPP2 IIN[1] IIN[2] IIN[3] PIN 17 42 50 62 67 1 10 20 41 51 60 70 54 45 48 HV 46 3 80 79 FUNCTION IIN[4] IIN[5] IREF IRQ ISINGP MDO[0] MDO[1] MDO[2] MDO[3] MDO[4] MDO[5] MDO[6] MDO[7] MDOEN MICLK 47 MOSTRT MOVAL PLL1 PLLGND PIN 78 77 27 57 28 59 61 63 64 65 66 68 69 71 14 MOC LK 76 72 23 22 FUNCTION PLLVDD QREF QSINGP RESET RREF STATUS TEST1 TEST2 TESTCLK VRB VRM VRT VDD CVDD VDD 58 VSS VSS XTI XTO PIN 21 34 33 49 38 52 39 40 16 35 32 26 13 55 73 VSS 56 74 18 19
14.0
MT312 Register Map
RADD is a virtual register with no address containing the address of the register to be accessed. It is written immediately after the 2-wire write address.
NAME RADD
ADR N/A
bit-7 IAI
bit-6 AD6
bit-5 AD5
bit-4 AD4
bit-3 AD3
bit-2 AD2
bit-1 AD1
bit-0 AD0 W
Def hex -
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Zarlink Semiconductor Inc.
MT312
14.1 Read/Write Register Map
Design Manual
Read/Write Register Map
NAME GPP_CTRL RESET DISEQC_MODE SYM_RATE_H SYM_RATE_L VIT_MODE QPSK_CTRL GO IE_QPSK_H IE_QPSK_M IE_QPSK_L IE_FEC FEC_STAT_EN SYS_CLK DISEQC_RATIO DISEQC_INSTR FR_LIM FR_OFF AGC_CTRL AGC_REF OP_CTRL FEC_SETUP MON_CTRL ADR 20 21 22 23 24 25 26 27 28 29 30 31 33 34 35 36 37 38 39 41 97 103 DIS_SR ERR_IND MIN_PULS_PER 312_EN DSS_B DSS_A Reserved Reserved Reserved AUT_IQ Reserved bit-7 Reserved FR_312 Reserved SEARCH bit-6 2W_PAS PR_312 HV SR_FMT V_IQ_SP CR_7/8 bit-5 bit-4 GPP_DIR[2:0] FR_QP PR_QP DISEQC INSTRuction length SYM_RATE[7:0] in MS/s (low byte) CR_6/7 CR_5/6 CR_3/4 CR_2/3 bit-3 bit-2 bit-1 GPP_PIN[2:0] 22kHz mode bit-0 Def Page hex R/W 20 R/W 00 R/W 1B R/W 80 CR_1/2 R/W 44 GO R/W 00 R/W 00 R/W 00 R/W 00 R/W 00 R/W 00 R/W 00 R/W 00 R/W 00 R/W 00 R/W 00 AGC_SL R/W 26 R/W 67 BA_LK[2:0] DS_LK[1:0] R/W 03 R/W 00 R/W 00 R/W 00 MAX_TONE_PER R/W D4 29 24 33 39 39 41 42 42 43 43 43 49 44 50 25 34 34 30 30 54 54 62 50 63 35 35 21
FR_VIT PR_VIT PR_BA
PR_DS R/W 00
SYM_RATE[13:8] in MS/s (high byte)
Q_IQ_SP Reserved Reserved Reserved AFC_M Reserved ROLL_20 R/W 00 Reserved IE_QPSK[23:16] Interrupt enable QPSK (high byte) IE_QPSK[15:8] Interrupt enable QPSK (middle byte) IE_QPSK[7:0] Interrupt enable QPSK (low byte) IE_FEC[7:0] Interrupt enable FEC
QPSK_STAT_EN 32
QPSK_STAT_EN[7:0] Enable various QPSK outputs on STATUS pin MOCLK_RATIO[3:0] SYS_CLK[7:0] - System clock frequency x2 in MHz DISEQC_RATIO[7:0] DISEQC_INSTRuction[7:0] FR_LIM[6:0] - Freq. Limit in MHz FR_OFF[7:0] - Freq. Offset in MHz AGC_SD[1:0] BSO AGC_BW[2:0] AGC_REF[7:0] AGC reference level ENCL_KO DIS_DS DIS_RS DIS_VIT EN_PRS Reserved DISEQC2_CTRL1 [7:8] TONE_EXT_PER BPSK
DS_Lock BA_lock VIT_lock BER_tog R/W 14
96 MANUAL MOCLK BKERIV MCLKINV EN_TEI
MON_CTRL[3:0] Monitor control
DISEQC2_CTRL1 121 DISEQC2_CTRL2 122 CONFIG 127
PLL_FACTOR[1:0] CRYS15 ADC EXT R/W 08
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Zarlink Semiconductor Inc.
MT312
14.2 Read Only Register Map
Design Manual
NAME QPSK_INT_H QPSK_INT_M QPSK_INT_L FEC_INT QPSK_STAT_H QPSK STAT L FEC_STATUS LNB_FREQ H LNB_FREQ L M_SNR_H M_SNR_L VIT_ERRCNT_H VIT_ERRCNT_M VIT_ERRCNT_L RS_BERCNT_H RS_BERCNT_M RS_BERCNT_L RS_UBC_H RS_UBC_L SIG_LEVEL AGC H AGC M AGC L FREQ_ERR1 H FREQ_ERR1 M FREQ_ERR1 L FREQ_ERR2 H FREQ_ERR2 L
ADR 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 108 109 110 111 112 113 114 115
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0 R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R
Def hex 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03
Page 45 45 45 51 47 47 50 31 31 52 52 52 52 52 53 53 53 53 53 55 55 55 55 31 31 31 31 31 48 48 37 38 38 48 48 25
QPSK_INT[23:16] Interrupt QPSK (high byte) QPSK_INT[15:8] Interrupt QPSK (middle byte) QPSK_INT[7:0] Interrupt QPSK (low byte) FEC_INT[7:0] Interrupt FEC QPSK_STATUS[15:8] (high byte) QPSK_STATUS[7:0] (low byte) FEC_STATUS[7:0] LNB_FREQ[15:8] Measured LNB frequency error (high byte) Reserved LNB_FREQ[7:0] Measured LNB frequency error (low byte) M_SNR[14:8] Measured SNR (high byte) M_SNR[7:0] Measured SNR (low byte) VIT_ERRCNT[23:16] - Viterbi error count (high byte) VIT_ERRCNT[15:8] - Viterbi error count (middle byte) VIT_ERRCNT[7:0] - Viterbi error count (low byte) RS_BERCNT[23:16] - Reed-Solomon bit errors corrected (high byte) RS_BERCNT[15:8] - Reed-Solomon bit errors corrected (middle byte) RS_BERCNT[7:0] - Reed-Solomon bit errors corrected (low byte) RS_UBC[15:8] - Reed-Solomon uncorrected block errors (high byte) RS_UBC[7:0] - Reed-Solomon uncorrected block errors (low byte) SIG_LEVEL[7:0] - Signal level at MT312 input AGC[23:16] - Front end AGC (high byte) AGC[15:8] - Front end AGC (middle byte) AGC[7:0] - Front end AGC (low byte) FREQ_ERR1[23:16] Input frequency error course (high byte) FREQ_ERR1[15:8] Input frequency error course (middle byte) FREQ_ERR1[7:0] Input frequency error course (low byte) FREQ_ERR2[15:8] Input frequency error fine (high byte) FREQ_ERR2[7:0] Input frequency error fine (low byte) SYM_RAT_OP[15:8] Symbol Rate Output (high byte) SYM_RAT_OP[7:0] Symbol Rate Output (low byte) DISEQC2_INT[7:0] DISEQC2_STATUS[7:0] DISEQC2_FIFO[7:0] MONITOR[15:8] Monitor (high byte) MONITOR[7:0] Monitor (low byte) ID[7:0] Chip identification.
SYM_RAT_OP_H 116 SYM_RAT_OP_L 117 DISEQC2_INT 118 DISEQC2_STAT 119 DISEQC2_FIFO 120 MONITOR_H MONITOR_L ID 123 124 126
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Zarlink Semiconductor Inc.
MT312
15.0 References
Design Manual
1. European Digital Video Broadcast Standard, ETS 300 421 December 1994. ETS Secretariat 06921 Sophia Antipolis Cedex France. 2. Digital Satellite Equipment Control (DiSEqCTM) EUTELSAT European Telecommunications Satellite Organisation 70, rue Balard - 75502 PARIS Cedex 15 France.
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Zarlink Semiconductor Inc.
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